Chip Tips #7: Transmission lines and termination
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- čas přidán 7. 04. 2018
- Transmission lines and termination used to be black magic. But I need to understand them because I'm building a bus and want good signal integrity. After studying transmission lines for a few days, I think I got the hang of it. This is my explanation of them with as little math as possible.
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I want to give you an extra thumbs up for the HP48 app and using metric
I'm halfway into the video and I have to say thank you so much for this amazing video. I'm really puzzled though with the number of views this video has. This video covers such an important and usually avoided, uncovered, or not understood subject that any electronics enthusiast would love to watch.
I wish I had been able to watch this 10 years ago when I was struggling to learn about this from textbooks and formulas alone
Very astounding how much effort you put in this video. It is the most thorough and clear explanation on transmission lines I've found on the web so far. Thanks for the great material!
It was perfect explanation, thank you, my friend:)
Just discovered your channel. Got so much to learn.
Awesome video man. I could have replaced my entire transmission lines course in university with this vid and would have been better off in the long run.
That spit swallowing is throwing me off! Lol.
Very interesting.
Thought I’d be learning about the electrical grid! This is nice too :-)
nice explanation I like the paper idea thanks for such information
A number of early parallel signal buses either were designed to subvert the reflection(by damping it), or in the case of PCI 1.0 took advantage of it.
im working on a circuit for remote (across the room) sensing... will be using a single (~10m) twisted pair for power and signal.. wonder how much of this that will show up..
10:48 Sorry I'm really just stuck. Why did you draw the electrons moving in the same direction as the current? Electrons move in the opposite direction of conventional current right?
Thank u
Water is interesting, because PCB materials like FR-2 or FR-4 are hygroscopic. That's why RF circuits use ceramic substrates.
Why do you count with dielectric constant of PCB when the field traveles in the wire?
Filip Miler the electric field is between two conductors, so it passes from the wire, through the PCB, and to the ground plane.
Awesome video! I'm currently building a CPU myself (although with HC-Logic) and started hitting those problems with reflections especially with my clock signal (although approaching a semi-stable state at ~1MHz). Now I'm curious, because your standard clock line looks more like a tree so I'd have multiple endpoints reflecting the signal. Does this mean that with for example two ends I will have a reflection with double the voltage at the driver?
I was thinking about using a series resistor for every line splitting of the main wire in the hope that they would create seperate transmission lines. Although I'm not quite convinced that this will completely please the signal gods.
Just something I wanted to point out. Clock frequency and rise time are different things. The Rise time of HC logic is 3.6ns which would require a bandwidth of 97Mhz. You can calculate the critical length following Robert's video to see if you need a series resistor. Just wanted to point that out even though I didn't answer your question.
Thanks for the answer! Yeah, I see the difference between clock frequency and rise time, but the circuit worked fine with the low clock frequency and ringing was not so much of a problem back then. But as I've increased the clock rate my ringing got worse as well, so I'd assume that the amount of crosstalk got intensified (do EM fields work like this? I seriously don't know, maybe it's time for a pcb with a ground plane...)
The critical length for HC would be ~54cm for ringing and ~27cm for crosstalk. I've just measured the longest clock line and with it's 43cm length it's sadly above the threshold.
The calculations given in the video were for FR-4 PCB. If you breadboard the circuit, (which you described), it would be totally different, (think about the parasitic effect of a breadboard).
I /think/, after spending some time fiddling with a diagram, that if you have a sender in the middle of a bus, and the sender has the series termination on it, then the signal gets launched both ways down the bus, they get reflected off the ends, and when each reflection gets back to the series termination, it is absorbed. So there /shouldn't/ be any additional reflections beyond the ones you want, but I'm not positive.
Also, the "stubs" that lead to the receivers all along the bus are also theoretically points where reflections will get generated. The only thing I've been able to find about that is "keep your stubs short", which kind of makes sense. In fact this is the sort of experiment I want to do for the next video.
The observation that ringing gets worse with rising clock frequency is interesting. Nothing that I know would account for that, except that possibly the ringing from the previous edge is still sloshing back and forth by the time your next edge occurs. That's just a guess. Another possibility is, if this is on a breadboard, you've got parasitics all over the place, and many of those parasitics just love to resonate at frequencies around 1MHz or above.
I've heard tell of people who happily run breadboarded circuits at 10MHz or above, but I don't know what techniques they use, and I wouldn't even try 1MHz on a breadboard. Run it slow to prove the concept, then start making PCBs for prototypes. They are so cheap now, that the only downside is the time it takes. I use JLCPCB which seems to have pretty good times to get back to California.
Lovely. But i'd hope the additive reflection doesn't actually damage the receiving chip thanks to ESD protection diodes on IO lines.
I am not sure that if 1V "suddenly" appear at the source, forgetting the Heavyside step function behavior (which is mathematical), 1 V would appear immediately on the wire: moving electrons will accumulate on the more positive tension and lack of electrons ( positive charges cannot move in a solid) will create itself a positive potential. In the resulting field, there will be less than 1V on the wire, at first. And when the reflection will come back, the total won't be 1V (in general), so at that time, it will be 'AS IF' a new tension would have suddenly appear, but that won't be 1V, and at each back and forth travel, we will finally ends up NOT to oscillation, but to gradually achieving less and less tension "instantaneously" appearing to become asymptotically equal to 1V, with time. I assume that it could also be like at 48:00 in you video, but in my case, it was always under the voltage, gradually filling up to the voltage of the source, with time (or a little bit like charging a capacitor).
That is what, at least, at the start, with a scope with 2 channels, and 30meter of wire. Install a probe at the start, and the other probe at 10m and return the wire at the source. Trigger on the first probe (raising at 1V level). Issue a 5V Heavyside Step. In my case, the first probe raise definitively less than 5V and the second probe see the raising around 65 ns later. It is only later on (when the field from the 20m collide back with the field having through the 10m of the probes, that things get mixed up. But DEFINITIVELY, if the pulse is at 5V, the first 65 nanoseconds don't see that full voltage (the raise time is around 6ns, in my case ).
Sometimes designers terminate buses without really understanding why - check out this example with the famed BBC Micro (go to 9:30) czcams.com/video/y4WG549i3YY/video.html
LOL! "Finger in the air engineering"