Excellent instruction for noobs, and even with 60 years experience I often pick up useful tips, tricks, and perspectives from your videos. Genuine high-content videos. Thanks.
Wow, a super-great video, for me. Being a self-taught hobbyist, I end up with big gaps in my learning curve. I have never seen caps/multiple caps explained this way = I grok! Brilliant! Kudos!
I got sidetracked into tank circuits while refurbishing a grid-dip meter. Characterizing the self resonant frequencies of capacitors and Inductors using the vna taught me a lot about taking measurements with the vna. Comparing theory to results, improving/finding limits of setup and the vna, and seeing different parasitic effects were very interesting for this beginner.
If you read the paper, the Guy, refers to, you'll read that the author points out that a VNA isn't good at measuring ESR. (A good LCR meter can give information about ESR... if that's important for the application... for example... bulk filtering.)
At 16:38 it is worth noting that the system has a decent Q, but not super high. I would assume the Q would measure higher in a setup that was not 50 Ohm. What i have also experienced from previous work, is that it is very likely that the circuit will have noise/oscillations at the peak (mkr 3) as the CLC circuit requires very little disturbance to oscillate. Some comments ask about the difference between dielectric, say X7R versus other MLCC, this should have a lesser degree of significance. The physical size of the package is what mattes the most, it is ultimately the loop area that causes the leakage inductance. Assuming same capacitance. When working with MLCCs, it is best to have as much capacitance for a given package as possible, There are however two things to remember 1) That x7r and the like will suffer from bias dependent capacitance. 2) via placement, trace length and pcb stack up will aslo be important for good decoupling.
Adding inductors in parallel will reduce the inductance. Using multiple vias to the ground and power planes on a multilayer will reduce inductance and improve noise. Everyone knows about bypassing Vcc but not many know about bypassing gnds to Vcc for really quiet boards.
Nice video, but it would have been nice if you had added a data point to the old discussion of what's better: A) N different value capacitors, or B) N of the largest value capacitor in parallel.
That depends on the application and product requirements, i.e. space, price, reliability, requirements for minimizing different component values, etc. Real-world engineering design work is always a balancing act. That was the part I most disliked. Now I do my own one-off designs and it's fun again.
Excellent, thanks for doing this experiment. It seems to shows that yes, indeed, 0.1uF was about the ideal value in the 1-3MHz clock frequency TTL digital logic days. And, that bypassing a 100MHz part on ground and power planes is likely to have a surprise lurking... A test fixture that has the typical surface mount 0603 part with it's 3 thermal tracks and a via might be interesting (I'm sure someone's done it).
You should try working at 10 Gigahertz which is the highest amateur radio band I operate on. 10 GHz is horribly sensitive. I can't even imagine RF labs that deal with 100 GHz. To say circuit board layout at those frequencies would be a nightmare would be my understatement of the year.
@@mikesradiorepair Oh, even oscillators at hundreds of Terahertz can be dealt with quite reliably in my experience - one click always turns the flashlight on, another turns it off... ;)))
So in the same way, when using a capacitor as power supply bypass/decoupling, the self-resonance would be reflective of the lower impedance and ability to source current to the power supply rail, as the device switches as whatever frequency. I guess its not accident these things are related (or identical) and now the connection is really clear. And how the bulk electrolytics can be further away to deal with low frequency power supply ripple, vs the higher frequency switching transients with capacitors right at the leads of the IC. I like it when things go click in my head like that.
On other thing to add...pick up a capacitor... any capacitor that you have... and say to your self... "You tricky little devil... you're not the 'capacitor model... however complicated' ...that I manage to conflate you with." In the long run... if they put you away (or on meds) for talk'n down to capacitors... you'll be safe... at least... from that conflation.
I can't resist quoting from The Art of Electronics, The X-Chapters (footnote 42, chapter 1x.3) regarding Z5U capacitors : "It is not clear to the authors why these capacitors even exist."
20:18 WEIRD! The curves overlap at the start until the SMD starts to jutt-right a little, which ultimately leads to its valley being far right of the leaded-cap. But that jutt-right appears to line-up with the beginning of the leaded-cap's inductive-curve! It's almost as though the SMD cap is being affected by inductance *earlier* than the leaded-cap, but since that inductance is so much lower, its effect is obviously less in the higher frequencies. Another way to look at it: If the leaded-cap's inductive-"only" curve were summed with what appears to be the leaded-cap's ideal capacitive-only curve (where at 8?MHz it reaches its valley, but if it were to *stay* there for all higher frequencies) then we'd see something like the SMD's curve. This must be a coincidence, eh? I can't think of how that would be the case physically/electrically (unless maybe the chip-capacitor is designed with "fingers" instead of plates, or maybe the inductive curve we see is actually calibration-error due to traces in both circuits?). Or it might just be a factor of zooming, where the leaded-cap also jutts-right around the same point, but does-so so shallowly that it can't be seen at this scale. It's weird how many things influence such measurements, and how we interpret them... I did [SO MANY] signal-integrity analysis simulations for DDR memory about two decades ago and found that even the tiniest changes, like shifting a via 1mm, would cause dramatic changes to the signal. Yet, the layout-standards documents were so loose, in comparison, that it's a wonder so many quickly/cheaply-designed motherboards worked at all! (nevermind DIMM sockets, etc.!). Simulations of "good layout"-practices often resulted in signals far outside the input-specs of the devices!
Extremely interesting, but I wonder a little what influence the 50 Ohm high-frequency measuring system has. In actual application you have a complex source, where capacitances and (line) inductances also have an effect and a load which its own impedance too..
I would like to see effect of using different values of capacitors together vs using the same value in parallel same number of times. New fpga designs use only one capacitor value but multiple times.
Now I understand better why different capacitors are put in parallel. I know it’s done in SMPS to remove high frequency noise because electrolytic caps do not handle the higher frequencies. I guess the short story that they tell us in electronics 101 that capacitors in parallel add to an equivalent Farad sum is not exactly true because it is highly frequency dependent.
Nice paper by the author(s) Stepins, et. al. Let's see if the Guy actually reads it. (Anyway, points out the limitation of using a VNA for measuring the ESR of a particular capacitor.)
I did read it. There are many calibration errors in 12-term calibrations of VNAs. I've considered doing a video on VNA calibration which I believe would be the first step if people want to read the Stepins paper. I did enjoy the discussion of different methods S11 S21 stuff. They were questions I had in my own head.
I am designing a PCB for my project it is a switch-mode power supply that has a switch-mode power converter an Atmel and a 12-bit ADC and it is really important to put a bunch of those decoupling caps near those components like the Atmel and especially the ADC in order to have really low ripple in the input I also would like to know how effective it would be to use frit beads alongside those decoupling capacitors
Hi, I saw a video where you hacked the E8357A VNA, I have one can you tell me how to extent the frequency and the time domain and if possible how to caibrate with the power sensors.
You designed nice fixture for measurement. Here is a trick I learned on the web, the mica capacitance deepest low changes with sound wave. Also, I saw in the paper you showed that at the deepest point shows the ESR; I wonder ESR of capacitor is the same throughout the frequency range? That is if we measure ESR of capacitor at DC with different method, is it going to be the same ESR at deepest -- Resonant -- point?
A most fascinating VNA capacitor video. Is it possible to use something like the $52 SEESII Nanovna-H Vector Network Analyzer, HW3.6 10KHz-1.5GHz for this example? Thank you.
What about MLCCs, I thought these were quite a big improvement in extending/spreading the dip, since they are lots of similar capacitors in parellel each with a small varience in inductance and resistance
S21 is the opposite of what was stated. Not that it makes much difference at these frequencies but you should use your test jig as OSL standard to eliminate the parasitics of the jig.
I agree you can calibrate out the small stuff if needed. A bit tricky to build a good OSL standard. as the S21 it is the forward transmission of a system. 1 is the input and 2 is the output. S21 points in the forward direction.
@IMSAIGuy Building a perfect standard is tricky but if your VNA allows to input standard coefficients and you have a set of known standards that you can use to characterize your DIY standards then it's not that hard.
@@IMSAIGuy I believe you have a friend that has access to a calibrated VNA? Make a "transfer standard". Lookup Kurt Poulsen guide on how to make your own standards. He posted it a few times on various groups, most recently on LibreVNA group. Since you have a lathe and a mill it should not be outside of your capabilities.
@@michaelg.5920 👍! I was using the loosely presented "F" to show it's the inverse function. And of course it's 1/(2*pi*C*freq). With Farads, functon f, Freq F, it seemed it might get a bit confusing... Thanks.
Excellent instruction for noobs, and even with 60 years experience I often pick up useful tips, tricks, and perspectives from your videos. Genuine high-content videos. Thanks.
Wow, a super-great video, for me. Being a self-taught hobbyist, I end up with big gaps in my learning curve. I have never seen caps/multiple caps explained this way = I grok! Brilliant! Kudos!
I got sidetracked into tank circuits while refurbishing a grid-dip meter. Characterizing the self resonant frequencies of capacitors and Inductors using the vna taught me a lot about taking measurements with the vna. Comparing theory to results, improving/finding limits of setup and the vna, and seeing different parasitic effects were very interesting for this beginner.
If you read the paper, the Guy, refers to, you'll read that the author points out that a VNA isn't good at measuring ESR. (A good LCR meter can give information about ESR... if that's important for the application... for example... bulk filtering.)
You’ve answered a question I’ve thought about many times
At 16:38 it is worth noting that the system has a decent Q, but not super high. I would assume the Q would measure higher in a setup that was not 50 Ohm.
What i have also experienced from previous work, is that it is very likely that the circuit will have noise/oscillations at the peak (mkr 3) as the CLC circuit requires very little disturbance to oscillate.
Some comments ask about the difference between dielectric, say X7R versus other MLCC, this should have a lesser degree of significance.
The physical size of the package is what mattes the most, it is ultimately the loop area that causes the leakage inductance. Assuming same capacitance.
When working with MLCCs, it is best to have as much capacitance for a given package as possible,
There are however two things to remember
1) That x7r and the like will suffer from bias dependent capacitance.
2) via placement, trace length and pcb stack up will aslo be important for good decoupling.
Adding inductors in parallel will reduce the inductance. Using multiple vias to the ground and power planes on a multilayer will reduce inductance and improve noise. Everyone knows about bypassing Vcc but not many know about bypassing gnds to Vcc for really quiet boards.
Just when you think you know a component ... Thanks for the dive down the bypass rabit hole .
Nice video, but it would have been nice if you had added a data point to the old discussion of what's better:
A) N different value capacitors, or
B) N of the largest value capacitor in parallel.
That depends on the application and product requirements, i.e. space, price, reliability, requirements for minimizing different component values, etc. Real-world engineering design work is always a balancing act. That was the part I most disliked. Now I do my own one-off designs and it's fun again.
Excellent, thanks for doing this experiment. It seems to shows that yes, indeed, 0.1uF was about the ideal value in the 1-3MHz clock frequency TTL digital logic days. And, that bypassing a 100MHz part on ground and power planes is likely to have a surprise lurking... A test fixture that has the typical surface mount 0603 part with it's 3 thermal tracks and a via might be interesting (I'm sure someone's done it).
Amazing what tiny bits of wire will do to your circuit at 10s of megahertz
Yup. Or a tiny bit of wire threaded through a single tiny ferrite bead. At DC, it's a short circuit - at 100MHz, it's 600 Ohms...
You should try working at 10 Gigahertz which is the highest amateur radio band I operate on. 10 GHz is horribly sensitive. I can't even imagine RF labs that deal with 100 GHz. To say circuit board layout at those frequencies would be a nightmare would be my understatement of the year.
@@mikesradiorepair Oh, even oscillators at hundreds of Terahertz can be dealt with quite reliably in my experience - one click always turns the flashlight on, another turns it off... ;)))
So in the same way, when using a capacitor as power supply bypass/decoupling, the self-resonance would be reflective of the lower impedance and ability to source current to the power supply rail, as the device switches as whatever frequency. I guess its not accident these things are related (or identical) and now the connection is really clear. And how the bulk electrolytics can be further away to deal with low frequency power supply ripple, vs the higher frequency switching transients with capacitors right at the leads of the IC. I like it when things go click in my head like that.
That's the difference between memorizing and learning.
You've got some serious gear. That HP network analyzer isn't cheap. I wish I could justify that cost.
czcams.com/video/Saob5r6nb_4/video.htmlsi=zypmFGOn9F6eoC5p
Always fun and educational. Thanks
Thank was very educational. Thank You
Great video. Thank you for this.
On other thing to add...pick up a capacitor... any capacitor that you have... and say to your self... "You tricky little devil... you're not the 'capacitor model... however complicated' ...that I manage to conflate you with." In the long run... if they put you away (or on meds) for talk'n down to capacitors... you'll be safe... at least... from that conflation.
A big old VNA, none of that nano rubbish, haha! Nicely explained and demonstrated.
go big or go home 😎
@@IMSAIGuy, I'm always at home now, so I have both. :)
BTW, I tend to use the 'rubbish' gear lately. It's usually more convenient and does the job.
Re: my rubbish gear
I console myself by remembering there is less warmup time required.
This stuff is super cool! Also another use for my nanoVNA 😁
Great video!!
Very interesting! Thank you
I would have loved to see an additional smd cap that was X7R instead of Z5U
I can't resist quoting from The Art of Electronics, The X-Chapters (footnote 42, chapter 1x.3) regarding Z5U capacitors : "It is not clear to the authors why these capacitors even exist."
I'd be interested to see the same tests with three lead caps.
20:18 WEIRD! The curves overlap at the start until the SMD starts to jutt-right a little, which ultimately leads to its valley being far right of the leaded-cap. But that jutt-right appears to line-up with the beginning of the leaded-cap's inductive-curve!
It's almost as though the SMD cap is being affected by inductance *earlier* than the leaded-cap, but since that inductance is so much lower, its effect is obviously less in the higher frequencies.
Another way to look at it: If the leaded-cap's inductive-"only" curve were summed with what appears to be the leaded-cap's ideal capacitive-only curve (where at 8?MHz it reaches its valley, but if it were to *stay* there for all higher frequencies) then we'd see something like the SMD's curve.
This must be a coincidence, eh? I can't think of how that would be the case physically/electrically (unless maybe the chip-capacitor is designed with "fingers" instead of plates, or maybe the inductive curve we see is actually calibration-error due to traces in both circuits?).
Or it might just be a factor of zooming, where the leaded-cap also jutts-right around the same point, but does-so so shallowly that it can't be seen at this scale.
It's weird how many things influence such measurements, and how we interpret them...
I did [SO MANY] signal-integrity analysis simulations for DDR memory about two decades ago and found that even the tiniest changes, like shifting a via 1mm, would cause dramatic changes to the signal. Yet, the layout-standards documents were so loose, in comparison, that it's a wonder so many quickly/cheaply-designed motherboards worked at all! (nevermind DIMM sockets, etc.!). Simulations of "good layout"-practices often resulted in signals far outside the input-specs of the devices!
This topic popped up on R3ddit a few days ago
More RF circuitry! Much more!
Extremely interesting, but I wonder a little what influence the 50 Ohm high-frequency measuring system has. In actual application you have a complex source, where capacitances and (line) inductances also have an effect and a load which its own impedance too..
you are right, one big issue is the PCB layout
I would like to see effect of using different values of capacitors together vs using the same value in parallel same number of times. New fpga designs use only one capacitor value but multiple times.
Now I understand better why different capacitors are put in parallel. I know it’s done in SMPS to remove high frequency noise because electrolytic caps do not handle the higher frequencies. I guess the short story that they tell us in electronics 101 that capacitors in parallel add to an equivalent Farad sum is not exactly true because it is highly frequency dependent.
The capacitor can not remove, dampen noise, only reduce the voltage.
Nice paper by the author(s) Stepins, et. al. Let's see if the Guy actually reads it. (Anyway, points out the limitation of using a VNA for measuring the ESR of a particular capacitor.)
I did read it. There are many calibration errors in 12-term calibrations of VNAs. I've considered doing a video on VNA calibration which I believe would be the first step if people want to read the Stepins paper. I did enjoy the discussion of different methods S11 S21 stuff. They were questions I had in my own head.
for those who want to read it:
www.researchgate.net/publication/269166796_Measuring_Capacitor_Parameters_Using_Vector_Network_Analyzers
It's a 1210 package that SMD capacitor.
Great video. How about checking S12 for a few scope probes?
already did: czcams.com/video/zlhKA5hpNOo/video.htmlsi=cTxdB75gbq11_0nI
I am designing a PCB for my project it is a switch-mode power supply that has a switch-mode power converter an Atmel and a 12-bit ADC and it is really important to put a bunch of those decoupling caps near those components like the Atmel and especially the ADC in order to have really low ripple in the input I also would like to know how effective it would be to use frit beads alongside those decoupling capacitors
a lot comes down to ground layout
Hi, I saw a video where you hacked the E8357A VNA, I have one can you tell me how to extent the frequency and the time domain and if possible how to caibrate with the power sensors.
You designed nice fixture for measurement.
Here is a trick I learned on the web, the mica capacitance deepest low changes with sound wave.
Also, I saw in the paper you showed that at the deepest point shows the ESR; I wonder ESR of capacitor is the same throughout the frequency range?
That is if we measure ESR of capacitor at DC with different method, is it going to be the same ESR at deepest -- Resonant -- point?
published ESR numbers are usually measured at the standard 100kHz. I showed here that is not the whole story.
@@IMSAIGuy Thanks for the info.
Get an LCR with multiple frequencies if you want to go down the esr rabbit hole.
A most fascinating VNA capacitor video. Is it possible to use something like the $52 SEESII Nanovna-H Vector Network Analyzer, HW3.6 10KHz-1.5GHz for this example? Thank you.
yes
So keeping the de-coupling cap as close as possible and with minimal leads will reduce this issue ?
yup
What about MLCCs, I thought these were quite a big improvement in extending/spreading the dip, since they are lots of similar capacitors in parellel each with a small varience in inductance and resistance
both of these are MLCC capacitors
@@IMSAIGuy Thank you
Please read "Myth of three capacitor values", Eric Bogatin, et Al, on Signal Integrity Journal.
too bad he didn't do measurements to compare with modeled. the newer multilayer small caps do a lot more than the old disks
Ok?
Z5U vs XR7?
S21 is the opposite of what was stated. Not that it makes much difference at these frequencies but you should use your test jig as OSL standard to eliminate the parasitics of the jig.
I agree you can calibrate out the small stuff if needed. A bit tricky to build a good OSL standard. as the S21 it is the forward transmission of a system. 1 is the input and 2 is the output. S21 points in the forward direction.
@IMSAIGuy Building a perfect standard is tricky but if your VNA allows to input standard coefficients and you have a set of known standards that you can use to characterize your DIY standards then it's not that hard.
@@galileo_rs I can't afford a calibration set. so I do the best I can
@@IMSAIGuy I believe you have a friend that has access to a calibrated VNA? Make a "transfer standard". Lookup Kurt Poulsen guide on how to make your own standards. He posted it a few times on various groups, most recently on LibreVNA group. Since you have a lathe and a mill it should not be outside of your capabilities.
I do not have access
R = f(1/F) ?
the reactance for the capacitor can be defined as: R = f(F) = 1/(2*pi*C*F)
@@michaelg.5920 👍! I was using the loosely presented "F" to show it's the inverse function. And of course it's 1/(2*pi*C*freq). With Farads, functon f, Freq F, it seemed it might get a bit confusing... Thanks.