8088 Processor Basic PC Memory Map and I/O Port Map

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  • čas přidán 5. 02. 2023
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Komentáře • 9

  • @freddyvretrozone2849
    @freddyvretrozone2849 Před rokem +1

    Hi,
    Nice Idea to do a quick review of all this.
    A0000 is VGA, then MDA B0000 and CGA B80000
    C0000 for Video ROM, then Other ROM.
    We can Add D0000 or E0000 for EMS
    Usable I/O Port are 12 Bit for XT, not 16 Bit

  • @stupossibleify
    @stupossibleify Před rokem +2

    Great summary, really enjoyed watching this. What would happen if you did place program code in CGA RAM, would you still be able to jump to and execute it even with some display corruption?

    • @elijahmmiller
      @elijahmmiller  Před rokem +1

      Generally speaking you should be able to put code in video memory and execute it. Same with the interrupt vector table. It would throw your interrupt pointers off.

  • @RafiStepanyan
    @RafiStepanyan Před rokem +1

    Thanks a lot for the great explanation! Very useful and interesting topic. What would happen with the reserved memory area if I have 1024Kb RAM instead of 640Kb?

    • @elijahmmiller
      @elijahmmiller  Před rokem +1

      It would overlap with the other memory. So like the BIOS, Video Memory, etc. Overlapping the BIOS would prevent it from booting up.
      On a None "PC" this can be done. Some of my early work had a straight 1024K of memory. I would upload the BIOS then reset the system. The 8088 ran fine but was not PC compatible. I have made a few videos on this channel about it.

  • @derre98
    @derre98 Před rokem +1

    Did you ever try running the Area 5150 demo with your DIY system? Does it work right for you?
    I built a system similar to yours and as far as I know, I have real 8088 and real MC6845, but while 90% of the demo works perfectly, there are these two scenes at the end of the demo, the "orc scene" and the "lake scene" where my monitor doesn't sync.
    I'm wondering if my monitor is at fault (PVM, not real CGA) or if it is related to the lack of DRAM and DMA controller, which might perhaps introduce some wait states or something that are not there with plain SRAM setup, and this then screws the cycle perfect trickery the demo might be doing. I also generated the OSC and the CLK with an FPGA to guarantee the signals are phase locked and even tried different phases, but that didn't seem to fix it.

    • @elijahmmiller
      @elijahmmiller  Před rokem +1

      I am uploading a DEMO of AREA5150. It does not work to well.

    • @derre98
      @derre98 Před rokem

      @@elijahmmiller Thanks, seems it works better for me then even though not all perfectly. I do get colors all the time and it syncs ok short of those two sections in the end.