COSIC seminar "Exploration of full-chip level SCA simulation" (Makoto Nagata and Kazuki Monta)

COSIC seminar - Exploration of full-chip level SCA simulation - Makoto Nagata and Kazuki Monta (Kobe University)
Generally, the tolerance of crypto modules implemented to application specific IC (ASIC) against side-channel (SC) attack is assessed after Si manufacturing stage. The first problem is that manufacturing ASIC chips is expensive and time-consuming. Moreover, if vulnerabilities are found at this stage, re-spin with countermeasures is required and it leads a large impact on cost and time. To avoid this problem, a Field Programmable Gate Array (FPGA) is often used instead of ASIC for the evaluation. But, the power consumption profiles of FPGAs and ASICs are different, even when executing the same cryptographic functions. The second problem is that post-silicon evaluation can evaluate whether the countermeasure is effective but cannot be used to explore a source of leakage when an unexpected leakage is found. So it is challenging for designers to add countermeasures at a re-spin stage.
Simulation-based SC leakage assessments is very important because it enables SC leakage evaluation before manufacturing and immediate revision if the desired SC leakage tolerance is not reached. However, at present, it has not reached a practical level due to issues with the accuracy and speed of the simulation. In this talk, we will introduce full-chip level simulation techniques of dynamic power, substrate voltage, and electromagnetic (EM) variations and explore the usage scenarios for SC leakage analysis over the full chip-package-system board (CPS) chain. Further, the gaps of simulation granularity, from transistor-level to CPS-level analysis will be discussed.