Register File Port PCB - Superscalar 8-Bit CPU #40
Vložit
- čas přidán 22. 07. 2024
- With the ALU finished it is finally time to move most of my homebrew CPU's breadboards onto dedicated PCBs. In this video we sketch out the first two backplanes of the CPU and plan which breadboards get turned into PCBs. We then design, layout, assemble, and test a first PCB for the register file ports.
This video series explores the concepts and techniques that make modern computer processors so incredibly fast and powerful. I build my very own 8-bit processor from individual logic gates and gradually evolve it to become a superscalar out-of-order machine. Along the way, we take a deep dive into contemporary computer architecture in a hands-on fashion and rediscover some of the foundations of modern computing.
Previous Video: • Adding Labels to My As...
Series Playlist: • Build a Superscalar CPU
GitHub Repository: github.com/fabianschuiki/supe...
Music:
- Korobeiniki by NoToneTyrone ( / free-epic-orchestral-t... ) licensed under CC BY-SA 3.0 (creativecommons.org/licenses/b...)
00:00 - Intro
01:33 - Backplane Planning
12:43 - Schematic
15:09 - Layout
19:29 - Assembly
21:29 - Soldering
22:40 - Testing
24:57 - Outro
#homebrew #8bit #breadboard #superscalar #computer - Věda a technologie
Ooh, I've been looking forward to the PCB-ification process. Also, loved the LED test haha. Great work!
Thanks 😃! Can't wait to get everything onto PCBs such that I can focus on fancier new things.
James Sharman started out with a hot air rework station but moved to a hotplate as it allows for finer heat control and the components don't go flying. Something to think about. And your LED function test was FANTASTIC!
He could go full Marco Reps and do whatever the hell it is he does in this video
czcams.com/video/D28uSzCs7-k/video.htmlsi=2APRJA3AfDym_uC4
Thanks 🙂! I'm definitely considering getting a hot plate for the soldering. Might do that sooner rather than later. And I had a lot of fun with the LED function test 😄
I love Marco Reps' channel. So many crazy builds and precision electronics 🤓. Absolutely fantastic.
I forgot, solder bridges on those resistor arrays, very common in James' videos.
@OscarSommerbo Pretty sure my clumsy solder paste application didn't help with that either 🫣
Very nice. Looking forward to the next episode comrade! 😜
😃 Thanks!
Style points for Korobeyniki! 😀
I couldn't resist 😃
The led test was great, loved it!
Haha thanks 😃 That was a lot of fun to do 😅
Simply wonderful, a master class in production 👏
Thank you very much 🙂!
Thanks for the huge smile you made me have :D
Very nice touch 😇
It’ll be interesting to watch you when this tiny computer of yours will make some sounds ;)
😃 Maybe it *does* need some sound output...
great work.
Thanks! 🙂
Thanks
New post for sanity. @weirdboyjim did use shadow ram in his build, he started talking about it in part 91 and then implemented it in parts 96 & 97. Assuming worst case scenario it takes 4.5 ish seconds to copy 64kb at 70ns, which might be acceptable, then James approach is simple and a very reasonable path to take. I wouldn't describe his method as DMA, at least not in the conventional sense, he just uses 4 counter ICs to step through the address range and copying as the counter race through the addresses. Using a battery powered SRAM chip, I think, is a more elegant solution, but it adds complexity, no doubt about that. Either way, I think it is a good approach to reduce the access time for the much slower EEPROM.
😃 That would be a very neat approach. I guess initially the 70ns ROM would also work directly as the decoder/program memory. And as soon as we get to some performance analysis and tweaking, an upgrade to an SRAM decoder would make sense.
@@fabianschuiki Looking into SRAM chips, apparently the leakage has almost been eliminated, negating the need for a battery backup to keep the data alive. But using the "Always copy on boot" like James does can be done rapidly using the ghetto DMA circuit he built.
I really go back and forth on the checking the SRAM for correct data. There are some fun stuff that can be made, like grouping functions by type in different regions and only update the regions that have changed. But for simplicity, at the cost of a few seconds of boot time the "always copy the entire rom" is hard to beat, and an additional benefit is that if we step through the entire address range we zero out the ram and put the computer in a known state. Which is nice when debugging the hardware.
@OscarSommerbo Yeah I really do like the ghetto DMA 😂👍👍👍
funny idea for testing! I know i'd have hooked up an arduino mega, and make it do a cylon eye (galactica) or kitt effect! haha
Haha, that would have been pretty neat as well 😃!
You can save some space there! Have you considered redesigning your register files so they slot on the edge, like a. NES cartridge? You can move the LEDs to the top edge so they are still visible, and use the L-shaped through hole jumper arrays so you can plug the register daughter boards into the back plane vertically.
That is a fantastic idea! 😀 I'm not entirely sure how bad things will get once we go dual-issue, but the number of chips for each register will roughly triple. That'll get a bit unwieldy in this flat build style, so making them vertical as you suggest would be a very nice solution. I do like the fact that you can see all ICs in this flat layout, but there's nothing too interesting about 16+ copies of the exact same set of register ICs... So maybe vertical it shall be? 😏
@@fabianschuiki The RC2014 uses 90 degree bent pins, rather than a slot. Might be cheaper and easier than card slots.
@@phookadude yeah card slots are difficult to comply with. Gold edge treating, precise PCB thickness etc. L-pins are easier
I wonder if you can get 45° pins? Then you could kind of "shingle" them and get the benefit of both a lower footprint while still being able to somewhat see the boards and ICs 🤔
My mind also immediately went to card edge connectors and card slots, but yeah, they can be pretty annoying. I like the idea of a 90° pin header though, or the shingles for extra awesomeness and style points 😎. For dual issue out-of-order execution, the registers will need 4 read ports and 4 write ports. That's 64 data lines... might be worth taking a regular two-row pin header and sandwich the PCB in between the rows, soldering have the connections on to one side, and the other half onto the other 🤔
Excellent 👌
Also, when you get round to the clock PCB, if you want to go with a pure logic build you can do it with just a pair of 2-input quad NAND gate ICs plus a few passives.
I think that given he is aiming for a superscalar design, the clock needs to be stable and predicable. While a Pierce oscillator could work, Fabian have already built the classical clock generator, that Ben Eater and James Sharman uses.
@@OscarSommerbonot even that complicated. Do away with the crystal and output cap, and use the 74hc132 Schmitt input NAND and you have a very stable relaxation oscillator that also has a very handy enable input. You can then use another one of the gates to debounce a push button for stepping (again with a ready built in enable) and you still handily have a gate left over for combining the outputs.
And those oscillators are every bit as stable as the 555 based circuits as they basically use the same idea.
@@JaenEngineeringevery home computer uses a Xtal. I don’t see why we need to do worse.
A relaxation oscillator like the 555 or a Schmitt trigger as you point out would definitely be nice to have on the clock PCB. 🤩
I was thinking about diving a little bit deeper into the whole frequency synthesis topic at that point and build up a PLL from discrete components on that PCB. I'd love to figure out what exactly the criticial path and its length is through the CPU, and then tune a clock to run the build as close to that upper limit as possible. It would be really cool if the CPU could write to a bunch of PLL registers to configure its own clock speed 🤓! That will still need a crystal reference oscillator. Could be a simple 1 MHz one though, since the PLL can synthesize a wide range of frequencies from that.
But that's just the free-running part. I'd still want to have a potentiometer-tunable oscillator and the manual stepping button. A Schmitt trigger might even be simpler or cleaner than a 555-based approach, because it can generate a nice triangle waveform compared to the 555's rather lopsided sawtooth-y wave.
@@fabianschuiki A tuneable PLL based clock sounds super cool!
What tool is used for the layout?
It's EasyEDA 🙂
@@fabianschuiki Thank you but I was asking about the tool you used for planning where component systems would go when using easyeda.
@pup4301 Ah sorry, I misunderstood. That's draw.io / diagrams.net. It's pretty convenient for architectural sketches and block diagrams 🙂
@@fabianschuiki Its okay I should have been more specific have a good day night or evening. It is 1am where I am. Late night work and all.
@pup4301 Oh yeah, 1am is definitely late 😴!
Not sure why, but that is one ugly pcb, the way the everything was routed just irks me, somehow placing the resistor networks at the sides of the buffers seems wrong, placing them on top and moving leds up would have looked better, but thats just ocd talking, also moving to tssop package would have helped, but those are notorious for getting solder bridges...
But all that beautiful space that would have been wasted by moving the LEDs up! 😏