13.9. Clock skew & jitter

A major assumption we made while calculating timing in a synchronous pipeline was that all registers observed the same clock. This is a gross oversimplification. Clocks will vary between registers due to delay on wires. This is a spatial effect called skew. Clock edges will also vary from cycle to cycle. This is a random temporal effect due to phase noise called clock jitter. Both effects can lead to uncalculated violations in a pipeline.

[@waterslager]

Very well explained. Thanks

[@rejilrajep3641]

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