Designing Binary Sequence Generators with Shift Registers

There are many applications for binary sequences including the Ethernet start of frame delimiter, frequency dividers, and pseudo random number generators. In this video, we present the steps used to design the feedback function for a shift register to create one of these sequences.
Timestamps
00:17 | Intro
01:46 | Divide by 5 Circuit Design
04:07 | Determining Number of Required Flip-Flops
05:52 | Determining the Shift Register Contents for the Divide by 5 Sequence
07:12 | Determining Shift Register Input to Drive the Divide by 5 Sequence
09:36 | Looking for Duplicate States in Shift Register Values
10:25 | Deriving Shift Register Input Logic for Divide by 5
12:53 | Drawing Ain Logic Circuit for Divide by 5
14:10 | Adding Failsafe Logic for the All-Zeros Case
15:58 | Error Code Sequence Example
17:09 | Determining Shift Register Contents for Error Code Sequence
19:15 | Determining Shift Register Input to Drive Error Code Sequence
20:04 | Deriving Shift Register Input Logic for Error Code Sequence
23:25 | Drawing Ain Logic Circuit for Error Code Sequence
Hashtags
#binary #sequence #generator

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[@VandalIO]

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