interesting video!! What we usually do is just increase the pad size of the components so that the added portion can act as a TP during Test. Please give your thoughts on this. Most fabricators should be able to probe the extended pads.
Yes they should have no problem with it, I asked Amit Bahl about this (from Sierra Circuits), he mentioned they will use just about anything as a test point if they need to, so if you push your manufacturer then an expanded pad should be fair game.
good video. In fact the test point mostly like an antenna which carries hi freq signals. I.e 1GHz. for least radio power lose & make sure the quality of signal, u need to(2 points) 1. the stub should has a length shorter than the 0.02 * wavelength i.e 1GHZ wave lengh = 300mm ,0.02 * 300mm = 6mm 2. the test point should be put with a full ground under or around it self. which make the electric field tightly constrained internally. ground layer under the signal layer will be a better choice. this 2 points make the test point stub a worst antenna which almostly emit no signals of any freq. thats a good high freq test point.
I saw next test point technique on some old PC's motherboards: just solder mask opening for 1-2 mm along the trace if this high speed trace is on top layer. I suppose it was done for flying probes testing.
@@magnuspihl6974 You can place those, just note the frequency of your signal. For digital interconnects running at high speed, it's better to just use a via along an interconnect or a pads at the endpoints to do continuity testing, but you wouldn't use that for ICT; for that you would want to find a via near the endpoints if possible. For an RF signal, that thick pad will be invisible to the signal unless the signal frequency gets really high. I'll actually create a video or article on this because it's a good exercise to see how input impedance is affected when you have a 1 mm pad on a thinner trace. On an RF line running somewhere at 2 GHz or higher, it's common practice to just remove the solder mask from the conductor because the solder mask is lossy, so that would give you probe access.
@@Zachariah-Peterson So a through hole on a high speed signal trace is the best way to debug it than to have a little testpoint which could have a big impact on input impedance ? Your channel is so nice for the young hardware engineer who I am.
I just depends how fast you mean by "high speed" I brought up a via along the interconnect just because you can use it for continuity if it was already there in the design, same goes for pads at the ends of an interconnect. For high speed signals, vias are generally not desirable on those routes if you can help it, but sometimes you don't have a choice because using vias is the only way to complete the route. To do ICT with high speed signals, best case is to use a wideband probe on a custom test fixture to probe exposed pins on components. If you can't do that and you already have a vi on the route, then use the via. For some packages, like BGAs, you have to use the vias and they will already be there for fanout routing. If no other options, maybe place a small pad. I like the idea of pulling back solder mask on high speed interconnects and using that to probe directly, but I've never done it myself.
Cool, although I also wanted to know how a pad on the trace would impact it. You talked about this type: __P__ However what about this type: ---O--- I use these for home etched boards to test and measure stuff, no high speed stuff, but still. Does that count as huge stubs on both sides? Hope you can understand it!
The --O-- type would be better for signal integrity since this would minimize the size of any stub that touches the trace. If the circular pad sticks out a little bit that is okay, it will act like a very small stub and would only affect really high speed signals. You could just remove some solder mask near the driver component also. I brought up a via if there was one already on the interconnect, you could use that as well. I would say to test it first though just to make sure you can get some signal into an oscilloscope. Also I do not know the bandwidth of probes used in ICT, if it is too low they may not be able to accurately reproduce the signal. Some companies like Tektronix make interposers specifically for some DDR memory packages and they essentially do the _P_ type test point at the load end of the interconnect (where the memory chip is), but you have to use a high bandwidth probe to capture all the frequency content that makes up the signal.
Normally you would place a differential probe across the pins of the transmitting or receiving component. You can place testpoints mid-way along the route if you want, which would then give you access to the same differential measurement. If it's a very fast interface, I think a better option is to remove the soldermask on the traces in the area you want to probe instead of placing large testpoints on each side of the route, that way you don't create a bandwidth-limiting measurement artifact mid-way through the interconnect. If the traces are very narrow (such as 2-3 mil wide on an HDI PCB), then you will have to place the larger test points and it will be difficult to get an accurate measure of the signal without it being degraded by the presence of the test points, this is why transmission line measurements for very high speed signals normally use a standard interface connection like SMA connectors so that a VNA could be used instead of scope probes.
Hi, thanks for the video. I followed your video and tried to turn a Via into a test point. Once I selected the Top for both Fabrication and Assembly in the Properties panel, the Testpoint Net Status under Testpoint Manager turned from "Incomplete" to "Illegal". Any thought?
Make sure you have set the correct design rules for test points. Just go into the PCB Rules and Constraints Editor, and search for "Test", the test point rules will come up and you will be able to set allowed test points in that dialog. The default minimum test point size allowance on that design rule is larger than the typical pad or via size in most PCBs, so make sure to set a higher minimum test point size. Once you change that minimum value so that it is smaller than your intended test point, the entry in the Test Point Manager will change from Illegal to Completed.
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thank you for another great video. those are really helping the community
Our pleasure!
interesting video!! What we usually do is just increase the pad size of the components so that the added portion can act as a TP during Test. Please give your thoughts on this. Most fabricators should be able to probe the extended pads.
Yes they should have no problem with it, I asked Amit Bahl about this (from Sierra Circuits), he mentioned they will use just about anything as a test point if they need to, so if you push your manufacturer then an expanded pad should be fair game.
good video. In fact the test point mostly like an antenna which carries hi freq signals. I.e 1GHz. for least radio power lose & make sure the quality of signal, u need to(2 points)
1. the stub should has a length shorter than the 0.02 * wavelength i.e 1GHZ wave lengh = 300mm ,0.02 * 300mm = 6mm
2. the test point should be put with a full ground under or around it self. which make the electric field tightly constrained internally. ground layer under the signal layer will be a better choice.
this 2 points make the test point stub a worst antenna which almostly emit no signals of any freq. thats a good high freq test point.
I saw next test point technique on some old PC's motherboards: just solder mask opening for 1-2 mm along the trace if this high speed trace is on top layer. I suppose it was done for flying probes testing.
I was just about to post the same as you. Or can't you place small testpoints (1mm diameter) on top of the traces?
@@magnuspihl6974 You can place those, just note the frequency of your signal. For digital interconnects running at high speed, it's better to just use a via along an interconnect or a pads at the endpoints to do continuity testing, but you wouldn't use that for ICT; for that you would want to find a via near the endpoints if possible. For an RF signal, that thick pad will be invisible to the signal unless the signal frequency gets really high. I'll actually create a video or article on this because it's a good exercise to see how input impedance is affected when you have a 1 mm pad on a thinner trace. On an RF line running somewhere at 2 GHz or higher, it's common practice to just remove the solder mask from the conductor because the solder mask is lossy, so that would give you probe access.
@@Zachariah-Peterson So a through hole on a high speed signal trace is the best way to debug it than to have a little testpoint which could have a big impact on input impedance ?
Your channel is so nice for the young hardware engineer who I am.
I just depends how fast you mean by "high speed"
I brought up a via along the interconnect just because you can use it for continuity if it was already there in the design, same goes for pads at the ends of an interconnect. For high speed signals, vias are generally not desirable on those routes if you can help it, but sometimes you don't have a choice because using vias is the only way to complete the route.
To do ICT with high speed signals, best case is to use a wideband probe on a custom test fixture to probe exposed pins on components. If you can't do that and you already have a vi on the route, then use the via. For some packages, like BGAs, you have to use the vias and they will already be there for fanout routing. If no other options, maybe place a small pad. I like the idea of pulling back solder mask on high speed interconnects and using that to probe directly, but I've never done it myself.
Cool, although I also wanted to know how a pad on the trace would impact it.
You talked about this type: __P__
However what about this type: ---O--- I use these for home etched boards to test and measure stuff, no high speed stuff, but still.
Does that count as huge stubs on both sides?
Hope you can understand it!
The --O-- type would be better for signal integrity since this would minimize the size of any stub that touches the trace. If the circular pad sticks out a little bit that is okay, it will act like a very small stub and would only affect really high speed signals. You could just remove some solder mask near the driver component also. I brought up a via if there was one already on the interconnect, you could use that as well. I would say to test it first though just to make sure you can get some signal into an oscilloscope. Also I do not know the bandwidth of probes used in ICT, if it is too low they may not be able to accurately reproduce the signal. Some companies like Tektronix make interposers specifically for some DDR memory packages and they essentially do the _P_ type test point at the load end of the interconnect (where the memory chip is), but you have to use a high bandwidth probe to capture all the frequency content that makes up the signal.
If we mirror the testpoint pads on both sides of the differential pair would that work? So one for + one for -. Same trace length and same pad size
Normally you would place a differential probe across the pins of the transmitting or receiving component. You can place testpoints mid-way along the route if you want, which would then give you access to the same differential measurement. If it's a very fast interface, I think a better option is to remove the soldermask on the traces in the area you want to probe instead of placing large testpoints on each side of the route, that way you don't create a bandwidth-limiting measurement artifact mid-way through the interconnect. If the traces are very narrow (such as 2-3 mil wide on an HDI PCB), then you will have to place the larger test points and it will be difficult to get an accurate measure of the signal without it being degraded by the presence of the test points, this is why transmission line measurements for very high speed signals normally use a standard interface connection like SMA connectors so that a VNA could be used instead of scope probes.
Do you have an recommendations for books or other learning sources for PCB design, rules, best practices ect.
Look up Altium Education, I wrote all of the coursework. You can sign up for free, you don't need to be a college student to use it.
Hi, thanks for the video. I followed your video and tried to turn a Via into a test point. Once I selected the Top for both Fabrication and Assembly in the Properties panel, the Testpoint Net Status under Testpoint Manager turned from "Incomplete" to "Illegal". Any thought?
Make sure you have set the correct design rules for test points. Just go into the PCB Rules and Constraints Editor, and search for "Test", the test point rules will come up and you will be able to set allowed test points in that dialog. The default minimum test point size allowance on that design rule is larger than the typical pad or via size in most PCBs, so make sure to set a higher minimum test point size. Once you change that minimum value so that it is smaller than your intended test point, the entry in the Test Point Manager will change from Illegal to Completed.
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