FSK Generator / Altera CPLD

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  • čas přidán 17. 07. 2024
  • This video will describe the workings of a Frequency Shift Keying generator and how to implement it on a CPLD. UART and Manchester encoding will be covered.
    High to low transition indicates the Start bit.
  • Věda a technologie

Komentáře • 29

  • @Massolese
    @Massolese Před 4 lety +5

    Your videos are always a treat to watch and very entertaining. I'm an automation engineering student and I love to see the history of digital electronics. My mind almost always goes straight to implementing something with microcontrollers, but seeing what you do so elegantly with discrete logic chips is truly fascinating. Greetings from Italy! xD

    • @0033mer
      @0033mer  Před 4 lety +1

      Thanks for the feedback.

  • @noweare1
    @noweare1 Před 4 lety +1

    Awesome video. I just started playing around with IR remote controls and I studied the library that came with arduino. IR comunications use the type of frequency shifting that you were explaining here. The decode was pretty interesting as it was done in software. An interrupt was set up to sample the incoming signal every 50us or so (i think) and count the number of intervals it was either high or low to determine if it was a high or low. Made me read up more on IR comms and it was said that technique also helped with interference from other light sources. There were some incredibly smart people back in the day.

  • @simplelyf4072
    @simplelyf4072 Před 4 lety

    Thanks for the variation in your videos from simpler to more complex and various topics !

  • @UndernetSystems
    @UndernetSystems Před 4 lety +1

    very cool video, thank you. I studied all these comm protocols in school and they are fun to mess with ☺️

  • @Gsus__17
    @Gsus__17 Před 4 lety

    Your videos are amazing

  • @tonykempson4331
    @tonykempson4331 Před 4 lety

    Thanks for another great video! I hope that this is a "primer" for LoRa/ FSK/OOK devices!

  • @kenappleman5444
    @kenappleman5444 Před 4 lety

    Very cool, thank you

  • @coxsj
    @coxsj Před 4 lety

    10:30...nowadays called a FRED or Flashing Rear End Device. Thanks for sharing. Very interesting.

  • @twobob
    @twobob Před 4 lety

    awesome.

  • @kryptocat4240
    @kryptocat4240 Před 4 lety +1

    Cool

  • @odissey2
    @odissey2 Před 4 lety

    Does PLL need some "primer" sacrifitial bits to lock-up, or it can grab incoming data starting the first bit?
    As seen on the scope, the output sine amplitude varies from the mark to space bits. How does this affect the PLL performance?

  • @MegaMino31
    @MegaMino31 Před 6 měsíci

    Can you make a video to explain how is the diode matrix is used?

  • @Enigma758
    @Enigma758 Před 3 lety

    Nice video, thanks. One question though, you lost me with "I'm using a diode matrix to divide down the crystal oscillator into audio frequencies". How can a diode matrix act as a frequency divider? (I understand how a ripple counter can do that, but not a diode matrix and google turns up no results). Thanks.

    • @0033mer
      @0033mer  Před 3 lety +1

      A ripple counter is a binary counter and also a binary divider which can divide by 1,2,4,8,16 ... etc. If we want to divide by 30 we would have to reset the counter after 30 input clocks and that is done by a diode matrix. If we connect a diode to each weighted output 2,4,8,16 and connect the anodes together with a pull-up resistor, this will give us a reset pulse after 30 input clocks. The diodes form a wired AND function and turn the ripple counter into a modulus divider. The divider in the CPLD is a modulus divider so it was easy to implement.

    • @Enigma758
      @Enigma758 Před 3 lety

      @@0033mer That's what I was missing, the diodes form a 4 input AND function to reset the counter. Thanks for clearing that up!

  • @FSK1138
    @FSK1138 Před rokem

    😎

  • @batman4e
    @batman4e Před 3 lety

    Hi, please, please, could you share how did you connect the crystal to XR2211 as I have never seen such an application. Certainly on the internet there is no such example (except here). I am using XR2211 and is drifting a lot, this could stabilize the XR2211.

  • @noweare1
    @noweare1 Před 4 lety

    Looking at the data sheet for the 4040 I am only seeing 1 input which is the clock. Since the chip is a 12 stage counter you can get 12 different frequencies out of it but I don't see how the uart input selects its particular frequency.

    • @0033mer
      @0033mer  Před 4 lety +1

      CD4040 is a binary ripple counter. We need a Modulus counter so a diode matrix is added. The diode matrix is controlled by the UART output which will reset the counter at the desired count. Probably would need a whole video to describe Modulus dividers.

  • @odissey2
    @odissey2 Před 4 lety

    I missed a step of controlling 4040 by the UART Tx. Some elements on the schematic 2:05 are absent.

    • @0033mer
      @0033mer  Před 4 lety

      I drew the schematic as a block diagram to make it simple and easy to understand. The UART data switches a diode matrix which controls the 4040 as a Modulo N counter. The UART data now switches between the programmed Mark/Space frequencies.

    • @odissey2
      @odissey2 Před 4 lety

      @@0033mer Thank you for reply. Is it possible to get MSK frequency shift using 4040 counter (e.g. 12001800Hz), or it is always 1 to 2 ratio (like 12002400Hz)?

  • @theengineer9910
    @theengineer9910 Před 4 lety

    Craziness