FSK Modulation and Demodulation
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- čas přidán 28. 08. 2024
- An explanation about FSK Modulation and Demodulation.
In this video, Gregory explains the full topology of an FSK demodulator, showing how the bitstream is recovered, how time is synchronized and frequencies offset are compensated.
FSK modulation encodes the data in shifts of frequency. In the case of binary signaling, two different frequencies are used, representing 0 and 1.
The process of demodulation is done using two NCOs - Numeric Controlled Oscillators - and average filters, actually implementing a sample-by-sample DFT in real-time.
The energies at the two different frequencies are compared to determine if the data bit is a 1 or a 0.
The continuous recovered bitstream is sampled with a NCO running at the baudrate and a Gardner Time Error Detector in conjunction with a PI controller corrects the sampling interval/point.
Frequency offset are compensated using a slow time-constant servo-loop that equalize average energy of the sampled points.
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A related video about Clock Recovery PLL:
• Clock Recovery and Syn...
Learn how a Costas Loop demodulator works for PSK modulations:
• Costas Loop Demodulator
Article about how DFT works:
gusbertianalog...
00:18 - Introduction
03:36 - Overall demodulator topology
06:15 - Detecting energy without filter (DFT)
10:38 - Quadrature detection topology
13:24 - Time Recovery/Synchronization
16:55 - Offset compensation/Carrier Recovery
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who's watching this genius in 2024? thanks Greg, you are the best!!
S2 S2
Great video. None of the other sources I've come across talk about the timing and frequency correction loops. This was just what I needed.
Thanks!
That was a pretty solid and straight forward presentation. Great work!
Thank you!
Gregory ..you are really a talented teacher...i have read a lot of books in communications and saw hundreds of videos from the Gurus ...and yet you are the best without any doubt....just a little note,,,, FSK sync can also be done by a matched filter that synchronizes with a chirp signal that preludes the message data stream ,of course the chirp must be added during the transmission....but hey this video is no different than your other excellent videos...well done...and in your words... it is really beautiful.
Thank you my friend!
Sir, you are a saviour..a big thanks from India👍👍
Awesome video, once again a pretty complex subject presented in a clear and engaging way. Makes me want to try and build one 😉
Let's build!! I only need 150GB for reinstalling Vivado 🤬😠
@@AllElectronicsChannel It is unbelievable how big the toolchains are! I've got my DE0 Nano lying around, but I'd probably have to add another hard drive to install Quartus.
Yep!! I Unbelievable
This doesn't look too demanding for a FPGA. I'm thinking about trying it with an Icestick and APIO, should save some space 😆
THE BEST YT CHANNEL TO LEARN RF!
😵😵😵
Super great video as always, lot of learning.
Just seeing this topic at school, maybe Ill try to implement it for the lab
Nice!
Very good explanation relating mathematical models to implementation.
Thank you! Welcome to the channel
This was awesome, thanks!
Thanks Archer!
What a complicated way to decode FSK. It was invented in the 1930... when no computer existed. The analog circuit used to decode FSK is very simple!
😜😜😜
Excellent presentation...
Thank you! Cheers!
TNX
Wow, that was a truly excellent presentation (love your enthusiasm !). I hadn't thought about the clipping trick (near 20:25).
As I understand it, it essentially means that we only need to consider the higher order bit of each input sample, right ? (I'm thinking saturated 8-bit signed values, so either +127 or -128).
Because assuming that it is the case, since quadrature demodulators essentially multiply the input signal by a couple of out-of-phase reference signals (sin & cos), maybe we can make these reference signals square as well. So we'd only need 1-bit multiplications, which is essentially what a XOR does (binary input signal XOR higher order bit of two pairs of counters running at F1 and F2, each one shifted by 90° with respect to the other).
It's super late here, and I'll have to give it more thought tomorrow but... I can see a bunch of neat optimization opportunities here, both for FPGA and CPU implementations.
In any case, you earned my subscribe :-)
Haha thanks man!
Yep, I nice trick is to use 4x oversampling..
Think of a sine/cos sampled 4 times per cycle. It will become a stream of 0 1 0 ‐1...
So this simplifies the multiplications a lot, needing only a mux that switches between the signal, 0 and the signal inverted.
The sin/cos relations will simplify to two streams 90deg out of phase!
1 0 -1 0
0 1 0 -1
I use this trick on a Speech Processor I designed, I have a video here on the channel, take a look 🙂
@@AllElectronicsChannel 4 x oversampling because it matches the length of the quaternary vectors [ 1 0 -1 0 ] (sin) and [ 0 1 0 -1 ] (cos). That's just brilliant.
Would be nice to do a follow up on a real FPGA implemention. Great contant!
great presentation! i wonder, is the explained method the principal of how a PLL works? or a freq discriminator?
No.. I have videos about PLLs here on the channel!
Wow ! I gotta think about this. I only need an fpga to make an fsk receiver !!! Even a 4fsk receiver like for WSPR ?
Nice, So PSK too has spectral leakage like discrete FSK ?
Yep! For commonly "bitstream" is filtered with a root raised cosine or gaussian filter to control the pulse shape/leakage
how led signal strength Meter works in old radios ?
I don't know!
@@AllElectronicsChannel Nice
Wow, Fourier transformation seemed like something only PhD people could understand, until this video.
Hahahahahahaha 😎😎
Very good content, keep it up! (but I should admit your English accent is like a torture)
Hahahaha! Thanks
p̶r̶o̶m̶o̶s̶m̶ 🤔