@@mindnova7850Doing so much with so much less is all about diminishing returns. The most influence on performance give parallel instruction execution that has hard limits due to data and control path dependencies in the programs. While core performance is no better than frequency multiplied by IPC. Frequency does not grow well. 2000 year CPUs had x5 less frequency than now. So the most performance gain had to cone from IPC grow. Was it at least x4 or worse since 2000 year?
I think the silicon industry is the equivalent of the modern space race. It just goes to show what insane advancements science can make with collaboration and a good amount of financial incentive behind it. It never ceases to amaze me how much further we can push this single element and I'm curious what will lie beyond the silicon lands.
this guy is just insane, being a Mat sci PhD student, I can resonate to how many hours of research and literature review goes into making one of these videos. Keep up the good work bro!
@@nostro1940 they didn't blow up your hut in the middle east yet, abu bakr? Guess you have a few more days with your goat. The pig is happy with your mother's services as well.
This channel has given me a passion for photolithography. I'm proud to say that as a second year student I'm currently interviewing with onSemi, microchip, synopsis and MKS thanks to the interest you sparked in me for this field
It's magic because it's proprietary and has less than 20% patents published, while 80% is simply under NDA. Then to send to this magical machine proper GDSII you HAVE TO pay $80,000 per SEAT each year to Cadence and Synopsys private IP mafia.
@@MicroageHD Well that's the last German engineering pride being left. Auto industry is in shambles, except the big three premium brands and Porsche the rest will go bankrupt soon, all the nuclear plants closed, no cheap gas and energy any more, you are finished. And you know, making incredibly smooth mirrors is not a rocket science. Chinese can already do it. They still don't have the rest of proprietary algorithms for control from ASML, but give them a few years and you'd be surprised when ASML is not a monopolist any more.
This is by far the best video from Asianometry. I thought the videos on High-NA EUV would have already been challenging, but looks like the bar is now raised even higher. Kudos to the great work. Looking forward to more videos with such high quality content.
For a couple of years I had been scratching my head trying to figure out how feature-sizes could be so much smaller than the wavelengths of light, even "extreme" UV. I met a guy in a brewpub that works for Nvidia who helped get some understanding but this added a bit more. Still learning. Thanks.
@@atharvabedarkar I think you need to look up the definition of the word "formerly". Here, I'll use it in a sentence for you to help "Intel was FORMERLY the leader in the industry. Now all the best people that FORMERLY worked at Intel all work somewhere else"
I speak native Spanish and I couldn’t make the reference until he mentioned it tbh. Probably because I only watch content in English and Spanish pronunciation doesn’t cross my mind ever
Mathematically, a lot of these computations are numerical inversions. OPC could be considered a crude numerical inversion depending on how it's done exactly. Typically, you have inputs and a mathematical model that gives an output. In an inversion, you know the output, but either the input or model is unknown. If the initial paper used simulated annealing, the computations most likely minimize the L2 norm, which is a classical numerical inversion technique. I imagine they have been predominately using Bayesian inversion in ILT. That gets very computationally intensive when you add complexity to Bayesian Inversion, but it is more flexible, and uncertainty quantification is given because the method involves probability distributions. I don't know what CuLitho uses, and it's hard to verify on the internet. I was thinking of AI Inference because NVIDIA has been using ML in GPU design recently. There are so many inverse problems in science. If it's a remote measurement or you are trying to determine the interior of an object from an exterior measurement, then it's most likely an inverse problem.
I appreciated your closing philosophical statement about using computers to design chips to make faster computers. It reminded me of the old "if you could make a machine that replicates itself but half the size, and the resulting machine does the same, how far could that recursion progress until the resulting machine is too small to work?"
It's worth mentioning that this will not have any kind of major impact on the actual throughput of the production of the wafers. There were some channels that saw this Nvidia breakthrough news and got carried away with the idea that throughput would be 10X faster or whatever. This will help speed up design, the throughput is still the same.
I was taking a VLSI course back in the early 80's, and for a class project had to write and use a LISP design rule checker. At work the lab next to me had a DEC minicomputer. I asked for several seconds of CPU time to verify my chip design. It actually took several hours of CPU time. Not exactly lithography, just a lesson about how much computational power is required to design even a VLSI sized chip.
Or perhaps your algorithm just wasn't very efficient? :) Funny that in the 80's taking a VLSI course meant writing your own DRC. When I took it (~2008) it was doing full custom transistor layouts, schematic capture, and a lot of timing analysis and spice simulations. Also measuring (in simulation) static and dynamic power consumption. Seeing as the cad tools haven't changed much since then (at least at the level of what's used in an intro class), I doubt it's changed much since I took it.
This video is a great introduction for laymen into the history of litho for wafer fab. Still a but technical on the jargon, but accessible to most who would pay attention.
Interesting comment about using computers to make computers faster. In 1978 my first job was making circuit boards for Motorola 6802 based industrial computer. It controlled a retrofit to a K&S 478 wirebonder making it automatic by targeting 2 points on the die and pushing the button. We had no drill for to make the PCBs so we took the computer we made and bolted on so big stepper motors and turned the wirebonder into a drill for the circuit boards. A vacuum cleaner was the dust collector. Our customers when the toured the factory would stop at this homemade hack of a machine, and ponder. Many commented "wow, the machine is making itself!" Indeed....
The more I learn about chip making from this channel the more I wonder if I might have been interested in the microelectronics engineering major over my computer engineering major. its all so fascinating, but I must stay faithful and true to my computer architecture & organization... and I don't think I could handle the circuits maths lol
Computers designing computers was the concept behind numbering "generations" of computers: 1st gen, vacuum tubes; 2nd gen: discrete semiconductors; 3rd gen SSI scale integration; 4th gen: LSI. Very self-referential. By now, it must be 20th gen or something.
I think we're still at 5th gen , 4th one should be VLSI, 5th being chiplets, which is work in progress... 6Th should be when were completely surrounded by computers in every day life in every tool we use... who knows...
Hope a video on chip architecture can be made. There was a video from CNBC (if I remember correctly) on ARM and how it moved forward when it's acqusition by NVIDIA was stopped by regulators.
Reminds me of the technique used for inter-chip communication on computer motherboards. Basically two chips "ping" each other and "learn" how to distort their own output so the receiving end gets the cleanest signal possible. -> Introduce distortions at the source so they overlap/interfere among themselves over the conductors path so the received signal is clean. It was probably Intel who developed this technique but I cant remember its name...
Isn't ILP the reason why Intel thought they had quad-patterning "solved" for their 10nm process, resulting in the disastrously late transition from 14nm many years later than initially announced ?
11:55 Manhattan Geometry refers to a regular grid of rectangles (typically squares, never triangles). It takes its name from the regular street grid pattern of most of Manhattan Island in New York City.
This is how I make sense of it. The fact that a photon is emitted from an individual atom implies the theoretical resolution limit of masks could reach the size of an individual atom regardless of the wavelength. (This assumes the etendue of the light source is the size of an individual atom). Working backwards, the photon wavefront emanating from the source atom must be duplicated at the absorbing atom. This is essentially what the mask design is trying to do. It’s more like a hologram than a stencil image being focused on the wafer. The wavefront reaching a point on the wafer must reach that point in phase from as large a solid angle as possible.
I just want to point out that depth of focus and depth of field are not the same.... at least in photography. Depth of focus relates to behind the lens, and depth of field relates to infront of the lens. A longer focal length with shallower depth of field will have a wider depth of focus.
I know this is besides the video and I'm sorry. But I love that you used a gif from Prodigal Son, I feel that it's a really great underappreciated series.
Immersion lithography is exactly the same concept that is used with light microscopes, when wanting to take a look at a sample of whatever under the highest magnification possible with light microscopes, it is common practice to place a small droplet of a very specific kind of oil, with a very specific refractive index, the light travels from the light source, underneath the sample, through the prepared sample on a glass slide with a thin cover slip of glass, the oil droplet contact both the top surface of the cover slip and also makes contact with the magnifying lens, the oil is carefully chosen so that the light rays basically pass right through the oil/glass interfaces without being wildly refracted, it's basically a clever way to collect and collimate limited light to provide more effective resolution at very high magnification, high for light microscopes at least.
I really like this discussion, and would love to know how these enhanced designs might actually impact the chip performance both computationally, power/heat, materials optimization. Additionally, going a bit deeper into the physics of how/why your enhanced designs look so radically more elegant than the non-enhanced versions. Thanks, Ken.
Quality content, as always. *sigh* Alright, I do recall back sometime Eeeh.. ‘99-01 ish, Intel’s Celeron, and in some iteration, CU interconnects were added Yes, it was referred to as the CUleron Yes, the jokes were made.
I feel a bit sad for Luminescent Technologies. Coming up with revolutionary idea 2 decades too early. Also I'm worried that it might cement NVIDIA's monopoly in some segments of GPU use (in this case I assume it's something like HPC). I really hope that not only Radeon Technologies, but also a lot of 3rd party companies are working on their own patents. And when it comes to RTG there is always a chance (given their record) that they will make it open source. Because unless CuLITHO (Or however NVIDIA spells it) is not monetized or restrictive in use (so proprietary with control over who can use it for what), then again, it might end up with monopoly. Then again - credit where credit is due - they have amazing researchers. And they deserve a praise (and raise).
@@rightwingsafetysquad9872 No. I hope they make great products. I just hope they don't get too many monopolies (it's almost guaranteed that they have or will have in some niches, but after it reaches critical mass, they won't care - look at their gaming GPU pricing. It is not "sane"). 2 different things.
NVidia's weight in HPC has become so enormous, this little niche of semiconductor design doesn't really move the needle much one way or another. AMD could get their shit together but doesn't; and of course there's Intel with Xeon Phi but they think that whoever hasn't run away to NVidia cannot move, that they have a captive customer base. I don't know that this sort of complacency is a good way to go about things, it usually doesn't end well. If anything this here goes to show why NV wins, because they keep pushing the field forward, they are not complacent not even for a second. Perhaps they deserve this monopoly, who knows, even though we all know it's not good.
11:02 at the edge of digital reality, certainty and uncertainty flip.. Great background setup to this point.. very cool to see people leveraging uncertainty. We just embrace the facts when it works.. otherwise insanity right ?
Interesting. I'm a little bit scared about how dominant NVIDIA became concerning anything GPU or AI related in the past few years, but you can't deny they're doing great work so far. Another thing: I'd like to know if NVIDIA thinks about nanoimprint lithography as well, as it seems this technology might take a decent portion of the market when it comes to older nodes, eventually. Great video as always!
nvidia mostly focuses on advanced nodes so i don't think they will consider nanoimprint lithography until it can beat EUV at those nodes with the same or better throughput and lower number of defects, with lower power consumption
Rumor is that if AMD failed in their next gen GPU, they will give up on the high-end GPU market. AMD is no match for Nvidia. We'll have to deal with this pseudo monopoly for a while.
I know virtually nothing about this field. My question is why not use an electron beam like an electron microscope instead of UV light? Can an electron beam be made smaller than the UV wavelength?
@@SoundsLegit71it can and has been done, problem is speed of manufacturing Electron beam is narrow and takes a long time to work over a modern silicon wafer which is 300mm radius or around 640cm2 in area for the current sizes Think of how many beams which manipulates at electron sizes parallely do you need to work on this to match 10 to 15 second exposure times (I am assuming this) per stage of a 8 or 15 stage process on an euv machine?
With silicon atoms being 0.2 nanometers, it's hard to understand how much further we could push silicon technology before having to jump to something like gallium nitride for improved frequency or power draw. There is only so far you can push new gate designs and better optical systems and even then, we're already hitting diminishing returns with heat and frequency.
Chip design and manufactoring are insane. They can make structures in atomic scale. How does the etching still work in the nanometer region? Liquids have a surface tension, how can they reach the desired points to etch?
Thank you for the video but there are still low frequency noises very hearable with good headphones (pop boomy sounds). They are distracting. Could you apply a high pass filter to audio during video editing please?
So far as I know, the primary company that makes the tools which can draw these pattern is IMS Nanofabrication, headquartered in Austria. Their Multi-Beam Mask Writers are revolutionary.
But surely, there are many common blocks used in a design, so their masks that can simply be called up from a library and used without extra computation ? Surely it would only be the new elements, and interconnections of "blocks" that actually need to be computed. Thank you for a fascinating video, I'd love more detail on the techniques , if they could be explained as clearly as you have managed here !
What you suggest was somewhat true when OPC was first introduced. If the distortion was caused only by the immediately adjacent features within the library cell (or block), then the appropriate OPC within each cell could be predetermined and replicated for each instance. But as feature sizes and separations continued to shrink for each generation, the "area of optical influence" continued to increase so that features of adjacent cells (and blocks) would affect each other. What you suggest is certainly true for memory products (which are highly repetitive) and is surely used by memory cell designers.
The thing is you just need one of each picture, 4 16 125, 2^2, 4^2, 5^3, thats not alot of pictures. Once you have the set of pictures, you must replicate the set of pictures. This way uses heavy radiation, or slow etching. Slow radiation has more spin charge, but goes a shorter distance. Like riding the motorcycle through the bee hive into the oblivion. Once a large amount of sets are produced, its taken to the stadium with the 215 ft curved reynolds wrap is gently glowin at 100 billion degrees. The aztec foot bed of graphite with the piano safety lights allows the workers to set the fuzed quartz down. The foolt path fills in with the layers 33 metal 35 alloy blend "glass" and a breeze washes over the field at 100 billion parts per 300 yards, its dealt it cuz you smlt it.
Why does the slide show 1:57 hopper 42x vs amper 23x wouldn't that just mean equal to ada love lace?? Cause if 3090 vs 4090 is uplift of 65% then hopper be around same ???? Just a question or it's more about there new way of processing and another reason to add $$ to price of chip?? Have a great day everyone.
I wonder what the optimizations would look like if you were to allow it to calculate in three dimensions 🤔 if the light isbeing focused down then seems to imply that it's coming into the design pattern from a spectrum of angles? So what if you printed a design image with a few layers? Could you account for the angle difference caused by the focusing to produce an anti-lensing effect, using kind of a shadow box design? Very interesting that these idealized patterns have kind of a morié a to them.
It's most likely to account for the effects of diffraction, that's why you get these kind of morie patterns. This is just my conjecture, but the principle of the fresnel zone plates might be coming into play here, where the mask itself is acting as a lens to focus light into the exact shape you want. Though disclaimer, I'm not an expert on this topic at all. Huygen Optics (the channel) has a really good video on this effect.
BEA Saleh... that name rang a bell. I went to rip out my old Photonics textbook that I haven't touched in almost a decade and it turns out that WAS the same Saleh! :D
I feels like some of this computation could be "cached" as reusable features. Additionally, simple proximity rules could probably be established for adjusting the ILT boundaries on a feature. That way you're essentially pre-calculating a lot of the work as you go. Then you'd only need to do a final pass for validation and adjustments to complex intersections.
Can you provide some link where the luminescent technology has been split into synopsys and KLA ? I see it's acquired by KLA. But no reference to synopsys at all.
I can't answer your question directly, but KLA is basically and inspection company (for masks and wafers) and Synopsis is an electronic design automation (EDA) company. Both companies need this software, as do their customers, circuit designers, mask shops, and wafer fabs. I'm sure KLA licenses this ILT software to all parties.
this reminds me of how precision improved in machining as machines would progressively build better machines. in the 90s, i heard an aside where Apple was supposedly designing its next Mac and sought to buy a Cray supercomputer to facilitate its design. Cray supposedly commented that he was designing his next Cray on a Mac. Circle of life stuff there. 😂
3:29 Actually, increasing k1 or lambda, or decreasing NA will yield better resolution, not just raising k1 or decreasing NA. The problem with raising lambda is one of overstimulation, which can be offset by lowering the amount of light projected.
11:01 Whoa! The 'ILT' yields totally non intuitive yet highly functional results. This leads one to speculate what 'Artificial Intelligence ' might yield: 1) The good: Even greater, yet less understood optimizations. 2) The bad: Maligned functionalities that only an AI 'being' can access, and will do so at a time of their choosing.
All the NVidia libraries start with CU for CUDA, (Compute Unified Device Architecture) their current overall parallel API and GPU architecture name, CUBLAS (basic linear algebra system), CUDNN (CU deep neural net) CUSPARSE (sparse array computation) etc., so the butt thing is an unfortunate coinkydink.
Seeking a bit more background on why this is so important. Wouldn't this process only need to be done once at the end of every chip design process? In which case, whilst faster is obviously better, it wouldn't make up a huge fraction of the overall chip design time?
I'm 32 and I would give my soul and sanity to go to school in electrical engineering just to participate as an underpaid intern in this industry. Photolithography is the most extreme manufacturing possible. How does Asianometry seem to know everything about the history, concepts, science, and terminology in the semiconductor industry? He sounds so young to know the equivalent of a veteran in the industry. Mindblowing.
Never really thought about, how the simulation time of a trillion triangles can have top down effects on everything silicon. I wonder how important this is in comparison to die shrinks? Could you more efficiently use an older node using better simulations? Is that what happened with Nvidia’s maxwell architecture?
12:56 One day we'll have in space fabs for chips. These will use lithography, but with a mask that is several hundreds of meters in size. The light will go through lenses similar in size to that of the mask, but these lenses will be fluid tension based, like almost completely self correcting. Spin fluid in space, and you get a lens, basically. Transistors operating on microvolts, 50 atoms wide circuitry. Makes Ryzen 9 appear like dinosaur bones when it comes to computational effectiveness.
50 atoms wide wires were already in use. 7 atoms have 1nm size. 50 atoms have 7nm size. This is what 7nm process is capable to print on Si. Now 3mm is in use that allows 20 atoms width wires.
The Vivek Singh in that paper was the same person. He was leading the computational lithography group at intel before he joined Nvidia.
I was in IC design from 5000 nm NMOS down through 65 nm CMOS. Thanks for catching me up on 2 decades of progress!
Older tech always fascinates me on how they can do so much with so much less.
@@mindnova7850Doing so much with so much less is all about diminishing returns.
The most influence on performance give parallel instruction execution that has hard limits due to data and control path dependencies in the programs. While core performance is no better than frequency multiplied by IPC. Frequency does not grow well. 2000 year CPUs had x5 less frequency than now. So the most performance gain had to cone from IPC grow. Was it at least x4 or worse since 2000 year?
I think the silicon industry is the equivalent of the modern space race. It just goes to show what insane advancements science can make with collaboration and a good amount of financial incentive behind it.
It never ceases to amaze me how much further we can push this single element and I'm curious what will lie beyond the silicon lands.
"Im curious what will lie beyond the silicon lands":
I think this will give you an Idea:
czcams.com/video/D--sSNKiVXg/video.htmlsi=duN1EHTAW4_9dpsg
A race to replace their jobs?😅
@@MilesBellas not needing to work???!!! such a bad future
this guy is just insane, being a Mat sci PhD student, I can resonate to how many hours of research and literature review goes into making one of these videos. Keep up the good work bro!
Do you think He does it alone? Ahahah. Budy, this is a whole team producing these videos.
So funny to see you jeets larping as outstanding math students
@@nostro1940stop it
@@nostro1940cope abdul 😂you abduls can only dream of going to Europe while drawing in mediterrean seas
@@nostro1940 they didn't blow up your hut in the middle east yet, abu bakr? Guess you have a few more days with your goat. The pig is happy with your mother's services as well.
I've seen every talk by Aki Fujimura about curvilinear masks. Being a mathematician, I find ILT the most fascinating part of chip manufacturing.
Thank you for another fantastic video Asianometry!! Your videos are some of my most beloved CZcams videos! Keep up the amazing work!!
This channel has given me a passion for photolithography. I'm proud to say that as a second year student I'm currently interviewing with onSemi, microchip, synopsis and MKS thanks to the interest you sparked in me for this field
What are you studying for this field exactly? Electrical engineering? Curious
Go get 'em tiger
@@user-gs8jv4oq6w
Lol, seconded.
Don’t forget to send him a Christmas present 😂❤
@@SimoneProvencherI study engineering physics
That lithography machine that ASML makes is literally magic to me
It's magic because it's proprietary and has less than 20% patents published, while 80% is simply under NDA. Then to send to this magical machine proper GDSII you HAVE TO pay $80,000 per SEAT each year to Cadence and Synopsys private IP mafia.
The main optical parts of these ASML machines are made by the company Zeiss in the black forest, Germany.
Did they have those lenses in the mid-1800s?@@MicroageHD
@@MicroageHD Well that's the last German engineering pride being left. Auto industry is in shambles, except the big three premium brands and Porsche the rest will go bankrupt soon, all the nuclear plants closed, no cheap gas and energy any more, you are finished.
And you know, making incredibly smooth mirrors is not a rocket science. Chinese can already do it. They still don't have the rest of proprietary algorithms for control from ASML, but give them a few years and you'd be surprised when ASML is not a monopolist any more.
@@perakojot6524 germany have 3 premium only so ??????
This is by far the best video from Asianometry. I thought the videos on High-NA EUV would have already been challenging, but looks like the bar is now raised even higher. Kudos to the great work. Looking forward to more videos with such high quality content.
the more i know the more fascinating it gets. thank you for producig this kind of videos!
For a couple of years I had been scratching my head trying to figure out how feature-sizes could be so much smaller than the wavelengths of light, even "extreme" UV. I met a guy in a brewpub that works for Nvidia who helped get some understanding but this added a bit more. Still learning. Thanks.
10:54 - Yes, Vivek was formerly the head of the computational lithography group at Intel.
Haha, pretty much anyone worthy of mention in the semiconductor industry is "FORMERLY" the head of something at Intel...
@@gorak9000 haha intel be finding some cool people then
@@atharvabedarkar I think you need to look up the definition of the word "formerly". Here, I'll use it in a sentence for you to help "Intel was FORMERLY the leader in the industry. Now all the best people that FORMERLY worked at Intel all work somewhere else"
@@gorak9000 lol, intel going down hard
These talks/explanations are fascinating. You do them well.
Good stuff here - your presentation is striking too - Thank you!
They definitely did have many of the world's 486+ million Spanish speakers talking about cuLitho...
We don't count economically, this is why they do it.
Or maybe they did!
I speak native Spanish and I couldn’t make the reference until he mentioned it tbh. Probably because I only watch content in English and Spanish pronunciation doesn’t cross my mind ever
JAJAJAJAAJAJAJ
seeing how nvidia basically sounds like spanish envidia (envy) and now culitho (small a55) I'd say they're sticking to their naming convention
Mathematically, a lot of these computations are numerical inversions. OPC could be considered a crude numerical inversion depending on how it's done exactly. Typically, you have inputs and a mathematical model that gives an output. In an inversion, you know the output, but either the input or model is unknown. If the initial paper used simulated annealing, the computations most likely minimize the L2 norm, which is a classical numerical inversion technique. I imagine they have been predominately using Bayesian inversion in ILT. That gets very computationally intensive when you add complexity to Bayesian Inversion, but it is more flexible, and uncertainty quantification is given because the method involves probability distributions. I don't know what CuLitho uses, and it's hard to verify on the internet. I was thinking of AI Inference because NVIDIA has been using ML in GPU design recently. There are so many inverse problems in science. If it's a remote measurement or you are trying to determine the interior of an object from an exterior measurement, then it's most likely an inverse problem.
I appreciated your closing philosophical statement about using computers to design chips to make faster computers. It reminded me of the old "if you could make a machine that replicates itself but half the size, and the resulting machine does the same, how far could that recursion progress until the resulting machine is too small to work?"
It's worth mentioning that this will not have any kind of major impact on the actual throughput of the production of the wafers. There were some channels that saw this Nvidia breakthrough news and got carried away with the idea that throughput would be 10X faster or whatever. This will help speed up design, the throughput is still the same.
thanks ,,,, all nvidia can do is talk ...
As an electrical engineer, this video is amazing because I'm currently trying to get into the IC industry. Thanks for the high-quality videos.
I was taking a VLSI course back in the early 80's, and for a class project had to write and use a LISP design rule checker. At work the lab next to me had a DEC minicomputer. I asked for several seconds of CPU time to verify my chip design. It actually took several hours of CPU time. Not exactly lithography, just a lesson about how much computational power is required to design even a VLSI sized chip.
Or perhaps your algorithm just wasn't very efficient? :) Funny that in the 80's taking a VLSI course meant writing your own DRC. When I took it (~2008) it was doing full custom transistor layouts, schematic capture, and a lot of timing analysis and spice simulations. Also measuring (in simulation) static and dynamic power consumption. Seeing as the cad tools haven't changed much since then (at least at the level of what's used in an intro class), I doubt it's changed much since I took it.
That plus LISP is really slow ;)
Probably because it has to parse a jillion brackets!@@MikeCampo
Yeah, you kids have everything handed to you on a silver platter.When I was your age I had to mine sand to make the silicon wafer!!! LOL@@gorak9000
(lisp expressions) use the same number of parentheses as function calls() in other languages.
This video is a great introduction for laymen into the history of litho for wafer fab. Still a but technical on the jargon, but accessible to most who would pay attention.
Agreed!
Interesting comment about using computers to make computers faster. In 1978 my first job was making circuit boards for Motorola 6802 based industrial computer. It controlled a retrofit to a K&S 478 wirebonder making it automatic by targeting 2 points on the die and pushing the button. We had no drill for to make the PCBs so we took the computer we made and bolted on so big stepper motors and turned the wirebonder into a drill for the circuit boards. A vacuum cleaner was the dust collector. Our customers when the toured the factory would stop at this homemade hack of a machine, and ponder. Many commented "wow, the machine is making itself!" Indeed....
Been waiting for this for a while. Thank you
One of my favorite movies is “Culito’s Way” with Ass Pachinko.
There is something very calming about your videos.
Your videos are just simply fascinating!
The more I learn about chip making from this channel the more I wonder if I might have been interested in the microelectronics engineering major over my computer engineering major. its all so fascinating, but I must stay faithful and true to my computer architecture & organization... and I don't think I could handle the circuits maths lol
can relate
Amazing work as always, sir!
Computers designing computers was the concept behind numbering "generations" of computers: 1st gen, vacuum tubes; 2nd gen: discrete semiconductors; 3rd gen SSI scale integration; 4th gen: LSI. Very self-referential. By now, it must be 20th gen or something.
You left out Konrad Suze.
I think we're still at 5th gen , 4th one should be VLSI, 5th being chiplets, which is work in progress...
6Th should be when were completely surrounded by computers in every day life in every tool we use... who knows...
How does Chip level Optical data ports fit into the architecture
@@scowell*Zuse
@@harshivpatel6238 6th: AI
Fascinating stuff!! Thank you!
"Let us dive in butt first... *But first* I want to remind you about the news letter"
I see you.
I seen an article about cannon having a new method competing with ASML as it costs a fraction of the costs.
I'm assuming you mean the nanoimprint lithography, John has already made a very interesting video about that
Hope a video on chip architecture can be made. There was a video from CNBC (if I remember correctly) on ARM and how it moved forward when it's acqusition by NVIDIA was stopped by regulators.
Nvidia can't make money trough the ARM consortium, regulators did a good job too, but it was the consortium themselves.
@@lucasrem ahh, ok. Thanks for the clarification
Unbelievable optimizations! Thank you for explaining it!
Fascinating presentation and topic. A fair bit is beyond my understanding, but it gave me a glimpse into the science of chip making. Very cool indeed.
Reminds me of the technique used for inter-chip communication on computer motherboards.
Basically two chips "ping" each other and "learn" how to distort their own output so the receiving end gets the cleanest signal possible.
-> Introduce distortions at the source so they overlap/interfere among themselves over the conductors path so the received signal is clean.
It was probably Intel who developed this technique but I cant remember its name...
Isn't ILP the reason why Intel thought they had quad-patterning "solved" for their 10nm process,
resulting in the disastrously late transition from 14nm many years later than initially announced ?
11:55 Manhattan Geometry refers to a regular grid of rectangles (typically squares, never triangles). It takes its name from the regular street grid pattern of most of Manhattan Island in New York City.
This is how I make sense of it. The fact that a photon is emitted from an individual atom implies the theoretical resolution limit of masks could reach the size of an individual atom regardless of the wavelength. (This assumes the etendue of the light source is the size of an individual atom). Working backwards, the photon wavefront emanating from the source atom must be duplicated at the absorbing atom. This is essentially what the mask design is trying to do. It’s more like a hologram than a stencil image being focused on the wafer. The wavefront reaching a point on the wafer must reach that point in phase from as large a solid angle as possible.
I just want to point out that depth of focus and depth of field are not the same.... at least in photography. Depth of focus relates to behind the lens, and depth of field relates to infront of the lens. A longer focal length with shallower depth of field will have a wider depth of focus.
I know this is besides the video and I'm sorry. But I love that you used a gif from Prodigal Son, I feel that it's a really great underappreciated series.
Immersion lithography is exactly the same concept that is used with light microscopes, when wanting to take a look at a sample of whatever under the highest magnification possible with light microscopes, it is common practice to place a small droplet of a very specific kind of oil, with a very specific refractive index, the light travels from the light source, underneath the sample, through the prepared sample on a glass slide with a thin cover slip of glass, the oil droplet contact both the top surface of the cover slip and also makes contact with the magnifying lens, the oil is carefully chosen so that the light rays basically pass right through the oil/glass interfaces without being wildly refracted, it's basically a clever way to collect and collimate limited light to provide more effective resolution at very high magnification, high for light microscopes at least.
I knew the word use 'Breakthrough' was a click-bait.
I really like this discussion, and would love to know how these enhanced designs might actually impact the chip performance both computationally, power/heat, materials optimization. Additionally, going a bit deeper into the physics of how/why your enhanced designs look so radically more elegant than the non-enhanced versions. Thanks, Ken.
keep doing this videos bro. awesome
Quality content, as always.
*sigh*
Alright, I do recall back sometime Eeeh.. ‘99-01 ish, Intel’s Celeron, and in some iteration, CU interconnects were added
Yes, it was referred to as the CUleron
Yes, the jokes were made.
centrino ?
seeing how nvidia basically sounds like spanish envidia (envy) and now culitho (small a55) I'd say they're sticking to their naming convention
Yep, that is literally the origin of the name. "invidia" is latin for envy. And their logo is green from the idiom "green with envy"
I feel a bit sad for Luminescent Technologies. Coming up with revolutionary idea 2 decades too early.
Also I'm worried that it might cement NVIDIA's monopoly in some segments of GPU use (in this case I assume it's something like HPC). I really hope that not only Radeon Technologies, but also a lot of 3rd party companies are working on their own patents. And when it comes to RTG there is always a chance (given their record) that they will make it open source. Because unless CuLITHO (Or however NVIDIA spells it) is not monetized or restrictive in use (so proprietary with control over who can use it for what), then again, it might end up with monopoly.
Then again - credit where credit is due - they have amazing researchers. And they deserve a praise (and raise).
this will definetely cement nvidia's monopoly. amd and intel need to step up their game
@@imeakdo7 Let's hope they do.
Can you really tell Nvidia to make worse products because monopolies are bad though?
@@rightwingsafetysquad9872 No. I hope they make great products. I just hope they don't get too many monopolies (it's almost guaranteed that they have or will have in some niches, but after it reaches critical mass, they won't care - look at their gaming GPU pricing. It is not "sane"). 2 different things.
NVidia's weight in HPC has become so enormous, this little niche of semiconductor design doesn't really move the needle much one way or another.
AMD could get their shit together but doesn't; and of course there's Intel with Xeon Phi but they think that whoever hasn't run away to NVidia cannot move, that they have a captive customer base. I don't know that this sort of complacency is a good way to go about things, it usually doesn't end well. If anything this here goes to show why NV wins, because they keep pushing the field forward, they are not complacent not even for a second. Perhaps they deserve this monopoly, who knows, even though we all know it's not good.
Nice channel, and nice explanation.
Very informative Nicejob
I'm only 45 seconds in and you already earned my like. Well done.
Great work, thank you
11:02 at the edge of digital reality, certainty and uncertainty flip..
Great background setup to this point.. very cool to see people leveraging uncertainty. We just embrace the facts when it works.. otherwise insanity right ?
Butt Culitho sounds like "culito" in spanish, *small butt* haha
Your picture should be in the dictionary next to the word "fastidious". Well done sir!
I did not expect this video to contain so many instances of the word butt, nor did I expect it to be said in the way it was 😅.
Just imagine if it had been talking about butt-er.
But what else could you expect but to take it to the extreme.
Let’s goo, another great video.
Thanks for, at the very intro, you addressed the meaning of "culitho" (culito) in spanish.
Interesting. I'm a little bit scared about how dominant NVIDIA became concerning anything GPU or AI related in the past few years, but you can't deny they're doing great work so far.
Another thing: I'd like to know if NVIDIA thinks about nanoimprint lithography as well, as it seems this technology might take a decent portion of the market when it comes to older nodes, eventually.
Great video as always!
nvidia mostly focuses on advanced nodes so i don't think they will consider nanoimprint lithography until it can beat EUV at those nodes with the same or better throughput and lower number of defects, with lower power consumption
Rumor is that if AMD failed in their next gen GPU, they will give up on the high-end GPU market. AMD is no match for Nvidia. We'll have to deal with this pseudo monopoly for a while.
AI is a joke kid.
I know virtually nothing about this field. My question is why not use an electron beam like an electron microscope instead of UV light? Can an electron beam be made smaller than the UV wavelength?
@@SoundsLegit71it can and has been done, problem is speed of manufacturing
Electron beam is narrow and takes a long time to work over a modern silicon wafer which is 300mm radius or around 640cm2 in area for the current sizes
Think of how many beams which manipulates at electron sizes parallely do you need to work on this to match 10 to 15 second exposure times (I am assuming this) per stage of a 8 or 15 stage process on an euv machine?
11:07 So this ILT is basically a hologram containing the desired image? Or a process of calculating such hologram?
With silicon atoms being 0.2 nanometers, it's hard to understand how much further we could push silicon technology before having to jump to something like gallium nitride for improved frequency or power draw. There is only so far you can push new gate designs and better optical systems and even then, we're already hitting diminishing returns with heat and frequency.
Yeah, its amazing ow much we were able to push it, and are still pusing. But something will have to give soon.
Chip design and manufactoring are insane. They can make structures in atomic scale. How does the etching still work in the nanometer region? Liquids have a surface tension, how can they reach the desired points to etch?
Thank you for the video but there are still low frequency noises very hearable with good headphones (pop boomy sounds). They are distracting. Could you apply a high pass filter to audio during video editing please?
I watched this to stimulate my brain, and I think I'm high from trying to understand what I was listening to. Well done.
Where is our CUDA for Xilinx/AMD Place and Route? Accelerating ASIC design and FPGAs don’t get any love haha
They have Rocm
@@imeakdo7 ROCm has a Place and Route solution?
I'm from Austria and I didn't know about IMS. What a pleasant surprise.
So far as I know, the primary company that makes the tools which can draw these pattern is IMS Nanofabrication, headquartered in Austria. Their Multi-Beam Mask Writers are revolutionary.
thanks :) missing this part in semiconductor industry.
wondering how I will be able to buy you coffee in Taipei as thank you gift haha.
this intro has been the funniest for me so far🤣
But surely, there are many common blocks used in a design, so their masks that can simply be called up from a library and used without extra computation ? Surely it would only be the new elements, and interconnections of "blocks" that actually need to be computed. Thank you for a fascinating video, I'd love more detail on the techniques , if they could be explained as clearly as you have managed here !
What you suggest was somewhat true when OPC was first introduced. If the distortion was caused only by the immediately adjacent features within the library cell (or block), then the appropriate OPC within each cell could be predetermined and replicated for each instance. But as feature sizes and separations continued to shrink for each generation, the "area of optical influence" continued to increase so that features of adjacent cells (and blocks) would affect each other. What you suggest is certainly true for memory products (which are highly repetitive) and is surely used by memory cell designers.
The thing is you just need one of each picture, 4 16 125, 2^2, 4^2, 5^3, thats not alot of pictures. Once you have the set of pictures, you must replicate the set of pictures. This way uses heavy radiation, or slow etching. Slow radiation has more spin charge, but goes a shorter distance. Like riding the motorcycle through the bee hive into the oblivion. Once a large amount of sets are produced, its taken to the stadium with the 215 ft curved reynolds wrap is gently glowin at 100 billion degrees. The aztec foot bed of graphite with the piano safety lights allows the workers to set the fuzed quartz down. The foolt path fills in with the layers 33 metal 35 alloy blend "glass" and a breeze washes over the field at 100 billion parts per 300 yards, its dealt it cuz you smlt it.
Why does the slide show 1:57 hopper 42x vs amper 23x wouldn't that just mean equal to ada love lace?? Cause if 3090 vs 4090 is uplift of 65% then hopper be around same ???? Just a question or it's more about there new way of processing and another reason to add $$ to price of chip?? Have a great day everyone.
We use the GPU to build the GPU.
That's how lathes are made, but someone had to build the first one from scratch pretty much 🤪
12:30 The way you say 2010s like it's the ancient past 😫😫
I wonder what the optimizations would look like if you were to allow it to calculate in three dimensions 🤔 if the light isbeing focused down then seems to imply that it's coming into the design pattern from a spectrum of angles? So what if you printed a design image with a few layers? Could you account for the angle difference caused by the focusing to produce an anti-lensing effect, using kind of a shadow box design? Very interesting that these idealized patterns have kind of a morié a to them.
It's most likely to account for the effects of diffraction, that's why you get these kind of morie patterns. This is just my conjecture, but the principle of the fresnel zone plates might be coming into play here, where the mask itself is acting as a lens to focus light into the exact shape you want. Though disclaimer, I'm not an expert on this topic at all. Huygen Optics (the channel) has a really good video on this effect.
Cool stuff. Great video
How do you know all this? Great topic.
I'm looking forward for their take on an ARM chip.
Cool. Thanks for sharing.
Fascinating, captain! 😊
BEA Saleh... that name rang a bell. I went to rip out my old Photonics textbook that I haven't touched in almost a decade and it turns out that WAS the same Saleh! :D
I feels like some of this computation could be "cached" as reusable features. Additionally, simple proximity rules could probably be established for adjusting the ILT boundaries on a feature. That way you're essentially pre-calculating a lot of the work as you go. Then you'd only need to do a final pass for validation and adjustments to complex intersections.
Already done in existing software.
Stable Diffusion's latest release, Cascade, is based on Würstchen (sausage) architecture too !!
😂
12:00 Manhattan geometry shapes are made of rectangles, not triangles
Sir Mix-a-Lot disapproves.
That git gud in the captions killed me LMAO
Can you provide some link where the luminescent technology has been split into synopsys and KLA ? I see it's acquired by KLA. But no reference to synopsys at all.
I can't answer your question directly, but KLA is basically and inspection company (for masks and wafers) and Synopsis is an electronic design automation (EDA) company. Both companies need this software, as do their customers, circuit designers, mask shops, and wafer fabs. I'm sure KLA licenses this ILT software to all parties.
Manhattan Layout predates VLSI. It originally referred to generic component layout on a PCB.
Steiner points locations, the algorithm used male these CPU design, emulating it to test it before you produce chips.
PCB? what did you meant ?
PCB refers to Printed Circuit Board @@lucasrem
this reminds me of how precision improved in machining as machines would progressively build better machines.
in the 90s, i heard an aside where Apple was supposedly designing its next Mac and sought to buy a Cray supercomputer to facilitate its design. Cray supposedly commented that he was designing his next Cray on a Mac.
Circle of life stuff there. 😂
3:29 Actually, increasing k1 or lambda, or decreasing NA will yield better resolution,
not just raising k1 or decreasing NA. The problem with raising lambda is one
of overstimulation, which can be offset by lowering the amount of light projected.
11:01 Whoa! The 'ILT' yields totally non intuitive yet highly functional results. This leads one to speculate what 'Artificial Intelligence ' might yield:
1) The good: Even greater, yet less understood optimizations.
2) The bad: Maligned functionalities that only an AI 'being' can access, and will do so at a time of their choosing.
I could improve this I bet. Already got ideas. I'd have to see the library though.
All the NVidia libraries start with CU for CUDA, (Compute Unified Device Architecture) their current overall parallel API and GPU architecture name, CUBLAS (basic linear algebra system), CUDNN (CU deep neural net) CUSPARSE (sparse array computation) etc., so the butt thing is an unfortunate coinkydink.
why you all cry about the name ?
@@lucasrem Why you wish to remain ignorant?
Or indeed fortunate.
Seeking a bit more background on why this is so important.
Wouldn't this process only need to be done once at the end of every chip design process? In which case, whilst faster is obviously better, it wouldn't make up a huge fraction of the overall chip design time?
On leading edge, say
I'm 32 and I would give my soul and sanity to go to school in electrical engineering just to participate as an underpaid intern in this industry. Photolithography is the most extreme manufacturing possible. How does Asianometry seem to know everything about the history, concepts, science, and terminology in the semiconductor industry? He sounds so young to know the equivalent of a veteran in the industry. Mindblowing.
Never really thought about, how the simulation time of a trillion triangles can have top down effects on everything silicon. I wonder how important this is in comparison to die shrinks? Could you more efficiently use an older node using better simulations? Is that what happened with Nvidia’s maxwell architecture?
your videos are really goood
Oopse, maybe I needed to start with the nice guy you mention at the beginning who makes simple videos. I got lost pretty quickly this time.
12:56 One day we'll have in space fabs for chips.
These will use lithography, but with a mask that is several hundreds of meters in size.
The light will go through lenses similar in size to that of the mask, but these
lenses will be fluid tension based, like almost completely self correcting.
Spin fluid in space, and you get a lens, basically.
Transistors operating on microvolts, 50 atoms wide circuitry.
Makes Ryzen 9 appear like dinosaur bones when it comes to computational effectiveness.
50 atoms wide wires were already in use. 7 atoms have 1nm size. 50 atoms have 7nm size. This is what 7nm process is capable to print on Si. Now 3mm is in use that allows 20 atoms width wires.
Into the light, I command thee demon chips!
On a serious note though, pretty good engineering!
Funneling spectrum of light into existence.
Computers making Computers, WHAT COULD GO WRONG?????? "Take my hand if you want to live.........."