To help this device work for RF radio applications, two things can improve current situation: 1. disable fractional mode to remove frac. spurs, 2. disable spread spectrum over SSEN pin and SSC_EN register bit by software. According datasheet, it's logical OR combination. This device can be configured as quadrature signal clock up to 115MHz which is suitable for quadrature receivers.
Your resurrection of the IC-245 is spectacular! I also have one, as well as the IC-255, 260, and 560 that may require this operation. Also, as a matter of interest, I obtained a Ten Tec Delta II the post office was kind enough to destroy the LCD display. So I've been considering replacing it with the LED style display and analog meter e.g. Ten Tec 516. Your instruction is really making me think all these projects are possible! Thanks again! 73, NG7I
PLLs almost always (perhaps always) have sidebands like your 1MHz spurs - that's the phase noise of the VCO being pushed out of the lock range of the PLL and into sidebands outside of the loop filter. At least, that's how it was explained to me (and remembered, so I could've misunderstood!) by an RF engineer coworker. PLL tuning can change the shape of the sidebands, but the total area is defined by how good/poor the VCO is.
A good VCO is always cleaner. That's what it's best at. However, a VCO drifts, and doesn't cover anything like the frequency range of an Si5351. I'm playing around with the 5351 now, and I thank you much for the clear description of what's going on with them. I'd been puzzling through the spec sheet for a couple of days with little luck. You explained it all in under 19 minutes. Working backwards from the frequency you actually wanted was so clear and simple that I just shook my head. Thanks also for noting that the 5351 has BOTH AM and FM distortion. That could be problematic in certain applications. I had expected the FM jitter from this sort of circuit, but the AM caught me off guard. It pays to watch your channel. Between a VCO and a digital clock generator (one that is, in this case equivalent to 3 separate VCO's,) each circuit has its own advantages and disadvantages. We just have to pick the one that's best for our application. I'd pay pretty good money for a circuit that was as good as both devices at the things they were each best at. But the government would far outbid me. :)
In my opinion, the extra 43 Hz that appear on the display of the frequency meter are not due to its decalibration (the frequency standard is with rubidium), but from the clock of SI 5351. The overwhelming majority of quartz crystals have a frequency slightly different from the one written on the case. If you measure, you will find this. A software patch must be applied.
Thanks for sharing! I've been wanting to look at the Si5351 and the Si4342 and ADF4351. There are some other around those number ranges chipsets that seem more interesting... though not certain the footprint will mount easy and mate up with the modules circuit design. Would be neat to see those all compared on a channel of a nice scope and spectrum analyzer to compare performance. Like you note also, compared with the stock VCO and your design too. Reads like the 4351 is the worst of them.
One big problem with that eBay / Ali express / Adafruit module (these use the 10 pin "A" version) - no transmit audio on FM, as that radio puts low level audio into the VCO control voltage to FM modulate the VCO on transmit. SSB will work though, it's injected elsewhere for that. For FM Tx, you need the 20 pin "B" version and the Tx audio (biased to 1/2 Vcc) fed into the "VC" pin.
Interesting video. Do you have any thoughts on an economical way to build a VHF SSB transceiver without needing to design a new PCB? I was considering using the SI5351 for this.
I'm curious of phase jitter of a PLL loop. Phase noise will appear as FM or PM at receiver. I guess, phase noise is limited to the loop bandwidth with higher frequencies getting diminished by the loop low pass filter.
It's a square wave output from the Si PLL/Clock chip... that and the jitter from factional division would mean it would have to have jitter cleaned and the fundamental filtered by downstream circuits, prior to going into the radio's mixer anyways... I agree that it's probably best to stick with the analong VCO that you have already. I'm guessing that you are playing around with a frequency counter add-on for your CPU controlled VCO now? Any issues with that Arduino's MCU clock interfering with RF and IF signals in the radio? I think it would be a 8 or 16 MHz crystal on that board... maybe need RF shielding down the road? Cheers,
I can't find that FM noise on any of my Si5351s here, though of course the spurs are present. The spurs are much less pronounced at HF (about 15dB lower on the one I have on my bench right now) than at the 2m band. Some of what you're seeing there is likely exacerbated by the breakout board design choices -- a tighter crystal will help. Heck, yours in the video isn't even a genuine one, so who knows what crappy crystal some race-to-the-bottom cloner put on there :-). I bet a fast buffer in front of it will kill a lot of the AM -- plus, a decent 5v logic buffer gives you a bit of a boost if you need more power out of it.
I just got a Si5351 breakout board and am trying to program it. I need 100MHz and 28.8 MHz for a project, and I get a warning that "Out0 [2..8MHz] and Out2[100MHz] May Have Coupling. What exactly are they warning me about? (The warning is from the ClockBuilderPro software that generates the register programming values for me.)
What is the easiest way to generate the maximum number of nth harmonica of a fundamental sine wave frequency? What if we generate all as square first and the convert to sine?
JUST a curiosity but have you considered adding an OCXO as your frequency standard instead of the cheap 25 MHz crystal? I've read that the requirements for the Si5351 are a suggestion, assuming one is using a cheap crystal but it actually works fine with 2-100 MHz, so the 10 MHz OCXO would likely be more stable than the standard 25 MHz crystal. For the given radio you are messing with, I'm not exactly sure what the point is, but if messing around for the sake of messing around, why not?
I think you've got it right. When I test my various Si5351s, they are in much better shape for HF with just a crystal. Pushing them up into VHF is closer to the edge, and will drive requirements for all the other parts to be nice and precise. A decent TCXO with narrow specs might even be fine, though an OCXO would certainly be nice if it's feasible.
They're useful chips but hard to FM so if the modulation for FM is applied to the VCO then it's a lot of effort. There is a version with a 'VCO' input which gives some limited capability and I believe it works reasonably, however they're not as easy to find breakouts for. Honestly, I'd be running with the board you have and experimenting with a PLL/VCO combo
@@agnelomascarenhas8990to achieve good FM many radios modulate the VCO, which you'd be replacing with the Si5351. An awful lot of radios run the VCO at final TX frequency so there's no "lower frequency" to "translate" either
I do something similar with 23 channel SSB CB radios to get the SSB channels 36-38 or even 10m, but just run it right into the crystal socket through a small balun. The original interstage transformers do a good job with spurs as far as I can tell with equipment on hand.
You can, but any fractional divider introduces lots of jitter. Since you can't really divide by a non-integer, what happens with a fractional divider such as your example there, is that it divides by 5 or 6; it uses the B/C ratio to decide that it'll count by that extra +1 for 5 out of every 9 cycles. That causes jitter. If you put all the jitter on the PLL divider and keep the multisynth divider a pure integer ratio, it's much less visible on the output because the PLL oscillator tends to smooth it out over time.
@@leonerduk yes, that's why I added a change / edit, a year ago. Multiplying by 34 and 5/9 is a closer match, and all the jitter is in the PLL section.
What you would expect! These chips are designed to replace TCXOs and XOs for clocking high speed stuff i.e. logic and things like that. When you use them for the intended purpose i.e. clocking something like an FPGA, then the harmonics and all the issues don't matter. They're rich in output harmonics because the datasheet actually talks about the output signal being a square wave. Back in the 90s you could get VCO modules that were surface mount that would produce much cleaner spectra anyways (hint- they were used extensively in GSM900 mobile phones)
To help this device work for RF radio applications, two things can improve current situation: 1. disable fractional mode to remove frac. spurs,
2. disable spread spectrum over SSEN pin and SSC_EN register bit by software. According datasheet, it's logical OR combination. This device can be configured as quadrature signal clock up to 115MHz which is suitable for quadrature receivers.
This was fascinating, thank-you! Now I understand a little more of how you program and get frequencies this way.
That was the best explanation I've heard for how the SI5351 derives it's output.
Thank you so much !!!
Your resurrection of the IC-245 is spectacular! I also have one, as well as the IC-255, 260, and 560 that may require this operation. Also, as a matter of interest, I obtained a Ten Tec Delta II the post office was kind enough to destroy the LCD display. So I've been considering replacing it with the LED style display and analog meter e.g. Ten Tec 516. Your instruction is really making me think all these projects are possible! Thanks again! 73, NG7I
PLLs almost always (perhaps always) have sidebands like your 1MHz spurs - that's the phase noise of the VCO being pushed out of the lock range of the PLL and into sidebands outside of the loop filter. At least, that's how it was explained to me (and remembered, so I could've misunderstood!) by an RF engineer coworker.
PLL tuning can change the shape of the sidebands, but the total area is defined by how good/poor the VCO is.
A good VCO is always cleaner. That's what it's best at. However, a VCO drifts, and doesn't cover anything like the frequency range of an Si5351.
I'm playing around with the 5351 now, and I thank you much for the clear description of what's going on with them. I'd been puzzling through the spec sheet for a couple of days with little luck. You explained it all in under 19 minutes. Working backwards from the frequency you actually wanted was so clear and simple that I just shook my head. Thanks also for noting that the 5351 has BOTH AM and FM distortion. That could be problematic in certain applications. I had expected the FM jitter from this sort of circuit, but the AM caught me off guard. It pays to watch your channel.
Between a VCO and a digital clock generator (one that is, in this case equivalent to 3 separate VCO's,) each circuit has its own advantages and disadvantages. We just have to pick the one that's best for our application. I'd pay pretty good money for a circuit that was as good as both devices at the things they were each best at. But the government would far outbid me. :)
In my opinion, the extra 43 Hz that appear on the display of the frequency meter are not due to its decalibration (the frequency standard is with rubidium), but from the clock of SI 5351. The overwhelming majority of quartz crystals have a frequency slightly different from the one written on the case. If you measure, you will find this. A software patch must be applied.
You're expanding my knowledge. Thanks.
Thanks for sharing! I've been wanting to look at the Si5351 and the Si4342 and ADF4351. There are some other around those number ranges chipsets that seem more interesting... though not certain the footprint will mount easy and mate up with the modules circuit design. Would be neat to see those all compared on a channel of a nice scope and spectrum analyzer to compare performance. Like you note also, compared with the stock VCO and your design too. Reads like the 4351 is the worst of them.
One big problem with that eBay / Ali express / Adafruit module (these use the 10 pin "A" version) - no transmit audio on FM, as that radio puts low level audio into the VCO control voltage to FM modulate the VCO on transmit. SSB will work though, it's injected elsewhere for that. For FM Tx, you need the 20 pin "B" version and the Tx audio (biased to 1/2 Vcc) fed into the "VC" pin.
Interesting video. Do you have any thoughts on an economical way to build a VHF SSB transceiver without needing to design a new PCB? I was considering using the SI5351 for this.
I'm curious of phase jitter of a PLL loop. Phase noise will appear as FM or PM at receiver.
I guess, phase noise is limited to the loop bandwidth with higher frequencies getting diminished by the loop low pass filter.
Use a bandpass filter buffered by an additional amplifier with negative feedback to provide some agc to smooth the AC jitter?
It's a square wave output from the Si PLL/Clock chip... that and the jitter from factional division would mean it would have to have jitter cleaned and the fundamental filtered by downstream circuits, prior to going into the radio's mixer anyways... I agree that it's probably best to stick with the analong VCO that you have already.
I'm guessing that you are playing around with a frequency counter add-on for your CPU controlled VCO now?
Any issues with that Arduino's MCU clock interfering with RF and IF signals in the radio? I think it would be a 8 or 16 MHz crystal on that board... maybe need RF shielding down the road?
Cheers,
I can't find that FM noise on any of my Si5351s here, though of course the spurs are present. The spurs are much less pronounced at HF (about 15dB lower on the one I have on my bench right now) than at the 2m band.
Some of what you're seeing there is likely exacerbated by the breakout board design choices -- a tighter crystal will help. Heck, yours in the video isn't even a genuine one, so who knows what crappy crystal some race-to-the-bottom cloner put on there :-).
I bet a fast buffer in front of it will kill a lot of the AM -- plus, a decent 5v logic buffer gives you a bit of a boost if you need more power out of it.
My experience is to use only one output of these si5351's using multiple outputs also generates a lot of spurs. Also good buffering is necessary.
Thanks for the info. I hadn't thought about the possibility of needing buffering. I'll look closely at the datasheet spec for output loading.
How do I output on clk 1. I want the output to be the displayed frequency -700hz so I can use it for a CW transceiver.
I just got a Si5351 breakout board and am trying to program it. I need 100MHz and 28.8 MHz for a project, and I get a warning that "Out0 [2..8MHz] and Out2[100MHz] May Have Coupling. What exactly are they warning me about? (The warning is from the ClockBuilderPro software that generates the register programming values for me.)
try calculate it manually, it is not too complicated
what is the name of the program that you reference to help you come up with the settings for the PLL?
rfzero.net/tutorials/si5351a/
What is the easiest way to generate the maximum number of nth harmonica of a fundamental sine wave frequency? What if we generate all as square first and the convert to sine?
czcams.com/video/h68iJ8JiHFQ/video.html
JUST a curiosity but have you considered adding an OCXO as your frequency standard instead of the cheap 25 MHz crystal? I've read that the requirements for the Si5351 are a suggestion, assuming one is using a cheap crystal but it actually works fine with 2-100 MHz, so the 10 MHz OCXO would likely be more stable than the standard 25 MHz crystal. For the given radio you are messing with, I'm not exactly sure what the point is, but if messing around for the sake of messing around, why not?
I think you've got it right. When I test my various Si5351s, they are in much better shape for HF with just a crystal. Pushing them up into VHF is closer to the edge, and will drive requirements for all the other parts to be nice and precise. A decent TCXO with narrow specs might even be fine, though an OCXO would certainly be nice if it's feasible.
You can clean the signal with a schmitt trigger and a low pass filter
They're useful chips but hard to FM so if the modulation for FM is applied to the VCO then it's a lot of effort.
There is a version with a 'VCO' input which gives some limited capability and I believe it works reasonably, however they're not as easy to find breakouts for.
Honestly, I'd be running with the board you have and experimenting with a PLL/VCO combo
You would FM a low frequency carrier and translate that to the desired band with the synthesized carrier.
@@agnelomascarenhas8990to achieve good FM many radios modulate the VCO, which you'd be replacing with the Si5351. An awful lot of radios run the VCO at final TX frequency so there's no "lower frequency" to "translate" either
Nice video, keep it up, thanks :)
Was it proper to use a 70mhz scope to measure 144mhz signal?
350mhz: czcams.com/video/eaoHYWYLRV0/video.html
I was thinking that the chip needs integers to stay clean.
I do something similar with 23 channel SSB CB radios to get the SSB channels 36-38 or even 10m, but just run it right into the crystal socket through a small balun. The original interstage transformers do a good job with spurs as far as I can tell with equipment on hand.
where is the micro controller code to control the chip?
get the library Adafruit_SI5351 then look at the example program
You could haved stayed by *32, and used a similar A + B/C to divide:
A=5, B=5, C=9 . 5 + 5/9 = 5.555556
EDIT: Change the multiply to 34 + 5/9 and your clock should get mighty close...
You can, but any fractional divider introduces lots of jitter. Since you can't really divide by a non-integer, what happens with a fractional divider such as your example there, is that it divides by 5 or 6; it uses the B/C ratio to decide that it'll count by that extra +1 for 5 out of every 9 cycles. That causes jitter.
If you put all the jitter on the PLL divider and keep the multisynth divider a pure integer ratio, it's much less visible on the output because the PLL oscillator tends to smooth it out over time.
@@leonerduk yes, that's why I added a change / edit, a year ago.
Multiplying by 34 and 5/9 is a closer match, and all the jitter is in the PLL section.
What you would expect!
These chips are designed to replace TCXOs and XOs for clocking high speed stuff i.e. logic and things like that. When you use them for the intended purpose i.e. clocking something like an FPGA, then the harmonics and all the issues don't matter.
They're rich in output harmonics because the datasheet actually talks about the output signal being a square wave.
Back in the 90s you could get VCO modules that were surface mount that would produce much cleaner spectra anyways (hint- they were used extensively in GSM900 mobile phones)