For explaining the code in detail, please have a look at the other videos in the playlist, e.g.: Circuit Architecture and FPGA Implementation Advanced VHDL Implementation Sigmoid Function and Exercises A VHDL basics tutorial is not the scope of this channel. I regret.
Dear proffesor, when increase the hidden layer, do we need to change the delay of the luminance level? I ran with two hidden layers, networkStructure is [3 7 7 2] and change connection[ ] to correspond to the output of NN but the result is not correct
Yes, you have to adapt the delay of the luminance. The neuron has a delay of 4 (?) cycles, so an additional layer increases the delay of the neural network by this number of cycles. I made a question mark behind the "4", because I have not verified this number. I'm 90% sure, but it could be 1 cycle more or less.
Best thing to do: Try it out by downloading the code and doing FPGA synthesis. The check computational resources, you can make a test run without pin constraints.
Thanks sharing this tutorial. Please make more videos on explaining the code in detail and VHDL basics tutorial.
For explaining the code in detail, please have a look at the other videos in the playlist, e.g.:
Circuit Architecture and FPGA Implementation
Advanced VHDL Implementation
Sigmoid Function and Exercises
A VHDL basics tutorial is not the scope of this channel. I regret.
Dear proffesor, when increase the hidden layer, do we need to change the delay of the luminance level?
I ran with two hidden layers, networkStructure is [3 7 7 2] and change connection[ ] to correspond to the output of NN but the result is not correct
Yes, you have to adapt the delay of the luminance. The neuron has a delay of 4 (?) cycles, so an additional layer increases the delay of the neural network by this number of cycles.
I made a question mark behind the "4", because I have not verified this number. I'm 90% sure, but it could be 1 cycle more or less.
really amazing
спасибо, хорошая работа
Amazing, I plan to implement on Max10 FPGA. Will the computational resources be sufficient?
Best thing to do: Try it out by downloading the code and doing FPGA synthesis. The check computational resources, you can make a test run without pin constraints.
Sir, I have a few question about machine learning on fpga , can I connect with you by using email ? Thank you , Sir
I regret, I can not provide individual tuition or consulting. Nevertheless, I try to answer specific question to the video lectures.