Thanks so much Robert for inviting me on and the wonderful chat we had! It was so nice to collaborate with someone who has the same passion for helping the EE community, albeit in different disciplines.
Hi @FPGAsforBeginners, thanks for sharing your experience. One question I had in mind. Why using raw sockets rather then udp ones ? Is it because of some checksum issues, or unexpected data in packet ?
I'm following you both but I wanted to say that you have a great chemistry for teaching digital electronics. I hope you will collaborate again in the future!
The moment you said that no IP blocks would be used, you got my full attention. Thank you so much for this informative and fun video. I have an Ultra96 V2 and some RMII Ethernet modules. Looks like I'll have to follow along.
Awesome. this You tube channel cs and electronics students must follow. the information we can grab from here is more than a text book. also he upload videos like this for free. you are awesome Robert.
for those who wants to repeat this wonderful course but their board do not have so many LEDs and buttons (I use qmtech kits very often for my tests), I propose to use the virtual input/output module from Xilinx IP list. From my side I might have some questions regarding SDIO PHY configuration interface. Since it was not used at all, I suspect it was used as it configures itselves in the negotiation sequence when the PHY was connected to the switch? In such case I can use any PHY ASIC? Even 1G if ASIC sustains the RMII communication option? How about if to connect directly to PC, and the PHY ASIC is able to detect the crossover cable, the configuration over SDIO bus still can be avoided or not?
Hi, I'm working with a zynq board implementing udp using the built in arm. I'm looking for an example implementing the software for the connection. My remote host is connected via a python socket, and I'm trying to correct for dropped packets. 🤔
IP does not show after adding repository... Not sure what is the issue. I can successfully add IP repo. But when click on + in the design, it will not list those. I tested in both 2023, 2024 version. Changed the board but still not working. Any help appriciated.
based on the example you can easily transport the data over local network to a standard PC/server and then run there an application to extract the data and do anything you need.
Usually for TCP/IP you would implement it purely using software on a softcore processor instead like a Microblaze or a hardcore processor like Zynq/Zynq US Processing System connected to an AXI crossbar.
from the design of implementation in this video, it may suspect that was used between 5K and 10K resources, but it can be less as well. If your tango has 20K no worry about
@@cccmmm1234 you can send the packets on something like spi and then to ther microcontroller do not solder your cat 5 or cat 6 cable to tang nano it will not be eletricalky correct
Thanks so much Robert for inviting me on and the wonderful chat we had! It was so nice to collaborate with someone who has the same passion for helping the EE community, albeit in different disciplines.
Thank you Stacey. I really enjoyed creating this video and learned a lot!
Hi @FPGAsforBeginners, thanks for sharing your experience. One question I had in mind. Why using raw sockets rather then udp ones ? Is it because of some checksum issues, or unexpected data in packet ?
You are always impressive Stacy. Thanks very much for this valuable information you really cleared a lot.
Stacey! You're awesome! :)
So cool that you are having Stacey on! She has great enthusiasm and is a good teacher!
the tutorial the FPGA student community deserves!
Thank you Robert for discovering talented people on CZcams and introducing them to beginners and engineers.
Stacey is the best ever, very important video as usual
I was litterally trying to do a project with Ethernet and a Spartan6, this was so helpful to understand the concepts
Yay Stacey! Her gentle enthusiasm and clear competence is wonderful
I'm following you both but I wanted to say that you have a great chemistry for teaching digital electronics. I hope you will collaborate again in the future!
That was great!
I've never touched FPGAs before, but this video makes them feel approachable.
Awesome video & collaboration! Great job Robert!
A dream come true please make more videos together. Wonderful (-;
This is why we've subscribed! Amazing!
The moment you said that no IP blocks would be used, you got my full attention.
Thank you so much for this informative and fun video.
I have an Ultra96 V2 and some RMII Ethernet modules. Looks like I'll have to follow along.
I love this so much. Very informative
Awesome. this You tube channel cs and electronics students must follow. the information we can grab from here is more than a text book. also he upload videos like this for free. you are awesome Robert.
Simply excellent ! Thanks
thank you for this educative video
Awesome collaboration. Both if you work well with other people.
Nice. Please make a video on designing custom IP modules in Xilinx Vivado.
Stacey has many examples on her channel.
Good tutorial
for those who wants to repeat this wonderful course but their board do not have so many LEDs and buttons (I use qmtech kits very often for my tests), I propose to use the virtual input/output module from Xilinx IP list. From my side I might have some questions regarding SDIO PHY configuration interface. Since it was not used at all, I suspect it was used as it configures itselves in the negotiation sequence when the PHY was connected to the switch? In such case I can use any PHY ASIC? Even 1G if ASIC sustains the RMII communication option? How about if to connect directly to PC, and the PHY ASIC is able to detect the crossover cable, the configuration over SDIO bus still can be avoided or not?
Good.
Great job!
🤩🤩
Most Excellent! I think FPGA's are a little bit neglected. Maybe because they're so complicated.
Hi, I'm working with a zynq board implementing udp using the built in arm. I'm looking for an example implementing the software for the connection. My remote host is connected via a python socket, and I'm trying to correct for dropped packets. 🤔
IP does not show after adding repository... Not sure what is the issue. I can successfully add IP repo. But when click on + in the design, it will not list those. I tested in both 2023, 2024 version. Changed the board but still not working. Any help appriciated.
OK, so this is the hardware part of Ethernet, but there still has to be some kind of software for a TCPIP stack to transport the data?
based on the example you can easily transport the data over local network to a standard PC/server and then run there an application to extract the data and do anything you need.
Usually for TCP/IP you would implement it purely using software on a softcore processor instead like a Microblaze or a hardcore processor like Zynq/Zynq US Processing System connected to an AXI crossbar.
I use Hercules and Wireshark
No there is no software. The FPGA itself forms up UDP packets and sends them, or receives and decodes them.
Is there anychange that this IP works for AES-ZUB-1CG-DK-G ?
Can I use this module with 2018.2 because I got some warnings problems.
Taking a new project back to 2018 m8ght cause problems. Try recreating the project from scratch and import the verilig files.
how to make it work for Arty A7 100t ? It does not have CPU_RESET pin
You can wire the reset to a constant of the right polarity.
how many luts does this project consume. how easy will it be to port to tang nano fpga
from the design of implementation in this video, it may suspect that was used between 5K and 10K resources, but it can be less as well. If your tango has 20K no worry about
Does the tango nano have RMII ethernet?
This example needs an RMII ethernet chip to actually send or receive ethernet.
@@cccmmm1234 you can send the packets on something like spi and then to ther microcontroller do not solder your cat 5 or cat 6 cable to tang nano it will not be eletricalky correct
@@aayush_deo_ranchi Sure you could potentially do that, but it would be kinda defeating the point...
@@cccmmm1234 what point is being defeated
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