High Speed and RF Design Considerations

Sdílet
Vložit
  • čas přidán 3. 08. 2024
  • At very high frequencies, every trace and pin is an RF emitter and receiver. If careful design practices are not followed, the unwanted signals can easily mask those a designer is trying to handle. The design choices begin at the architecture level and extend down to submillimeter placement of traces. There are tried and proven techniques for managing this process. The practical issues of real system design are covered in this session, along with ways to minimize signal degradation in the RF environment.
    Presented by: Zoltan Frasch, Senior Applications Engineer
  • Věda a technologie

Komentáře • 33

  • @diggleboy
    @diggleboy Před 4 lety +4

    Wow! That was the most comprehensive RF PCB design and component layout lecture I've ever seen!
    Thank you Zoltan Frasch, Senior Applications Engineer, for putting this together. Makes the planning all more important before cutting the schematic.
    There is a process and order of that process for sure in RF circuit design and this video helped me learn more of what to add to my already existing process. Thanks!
    I'll definitely re-watch this video several times to burn it into my consciousness to include it in my RF circuit design process.

  • @navadeep.ganesh
    @navadeep.ganesh Před 3 lety +4

    Very insightful! It takes long term experience to realize these otherwise.

  • @vejymonsta3006
    @vejymonsta3006 Před 4 lety +2

    Lots of useful and information in here for good PCB design in general. Not just for high speed or RF!

  • @PratikRocksable
    @PratikRocksable Před 7 lety +43

    5yr knowledge in 45 min

  • @annacersongor8553
    @annacersongor8553 Před 3 lety +4

    So Munch info, great tuto, thanks forum sharing, thumbs up.

  • @gideonmugo5797
    @gideonmugo5797 Před 3 lety +2

    Great video. Great content. I've really learnt a lot. Thank you.

  • @mohamedtebbo7315
    @mohamedtebbo7315 Před 2 lety +1

    Took me forever to find this!!

  • @tseckwr3783
    @tseckwr3783 Před 6 lety +2

    Excellent presentation!

  • @LydellAaron
    @LydellAaron Před 3 lety +1

    Best video gem right here.

  • @raushanyadav2076
    @raushanyadav2076 Před 6 lety +1

    thank you sir for uploading video....

  • @ashishkushwaha5770
    @ashishkushwaha5770 Před 8 lety +6

    thanks for making this video .

  • @chienthanhnguyen2268
    @chienthanhnguyen2268 Před 6 lety +2

    I wish I have your knowledge on the PCB design for rf applications!

  • @djadostyle
    @djadostyle Před 4 lety

    very usefull, thanks @Analog Devices

  • @gawedalameri1593
    @gawedalameri1593 Před 9 lety +1

    thank you

  • @HamzaHamza-ny5pr
    @HamzaHamza-ny5pr Před 5 lety +3

    Hello,
    I have a question for you as an expert, what do you say about separating the analog ground area to the digital ground area with a gap, this means that the return currents will not share the same ground plane,
    However i had watched a video says that this can cause a differential potential of 1 mvolt between the two ground areas (planes) and hince the external connectors will radiate and hince a failure to meet with EMC requirements?
    thanks in advance !

    • @Jarrettmonty99
      @Jarrettmonty99 Před 2 lety

      This is old but maybe someone else in the future will reply. From my understanding, no designer in this age will tell you to split the ground planes.. Everyone says you want solid ground plane, just "isolate" (split) the digital and analog sections. I have no idea why they say this, but I've only really seen this split plane idea peddled by datasheets/semiconductor manufacturers in general. Almost a theorist/experimentalist debate. Obviously, they should know their stuff, but I'm wondering if it's just an oldage that may have been fine in the 10s of MHz, but not in the modern era with GHz abundant. But I have very little experience myself to comment for sure.

  • @simonndungu1196
    @simonndungu1196 Před 5 lety

    cool stuff

  • @mikal_1
    @mikal_1 Před 4 lety +1

    I am a bit confused, please give me some guidance, sir.
    @32:47, X = Copper length (mm) and Y = Copper width (mm),
    but @33:25 you say "minimize inductance: increase trace/pad WIDTH"
    Now my confusion: For a SOIC the X = 0.51 mm and for a 3x3 mm CSP the X = 0.6 mm (so the length has increased)
    So it seems the X (which was labelled as the LENGTH earlier) has increased and the inductance decreased from 0.08 nH to 0.05 nH. So the X would be the width, not the length right?
    Please help. Thank you very much for the video.

  • @yangwang3707
    @yangwang3707 Před 6 lety

    Does anyone know where can I find the slides? Thanks.

    • @analogdevicesinc
      @analogdevicesinc  Před 6 lety

      Hello, this was uploaded about 4.5 years ago and the slides are not available. But, we have many articles located on our Analog Dialogue site. Here is a link that searches for "rf design" www.analog.com/en/analog-dialogue/search.html?q=rf%20design

  • @torocsikm89
    @torocsikm89 Před 8 lety +5

    Dat accent! :D
    BTW great vid!

    • @shlooky1
      @shlooky1 Před 8 lety

      +torocsikm89 hungarian ;)

  • @ponravka
    @ponravka Před 7 lety +4

    There are too many basic things. I feel like at a lecture for Economists or other non-electronics. A more fitting name for this video would be How to make a PCB and some high speed and RF Design...

  • @nasermasri3816
    @nasermasri3816 Před 4 lety

    TOP TTOP TOP8

  • @neuralnetwork653
    @neuralnetwork653 Před 7 lety +1

    Попытались за 40 минут упомянуть обо всем, в итоге видео вышло вообще ни о чем.... у AD вообще с обучающими видео беда.