JFET: Construction and Working Explained
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- čas přidán 27. 07. 2024
- In this video, the construction and working of n-channel JFET and p-channel JFET are explained.
By watching this video, you will learn the following topics:
1:01 Construction of n-channel JFET
2:25 Working of n-channel JFET
6:01 Output characteristics (Drain curves) of n-channel JFET
11:07 Different regions of operation of JFET
13:07 p-channel JFET
14:44 Symbols of n-channel and p-channel JFET
JFET (Junction Field Effect Transistor) :
The junction field Effect Transistor (JFET) is used in a wide range of applications. It is a three terminal device. (The 3 terminals are Gate, Drain, and Source)
JFET can be classified as either n-channel JFET or p-channel JFET.
n-channel JFET:
In the n-channel JFET, the channel is made up of n-type semiconductor material and two small p-type regions are formed near the channel.
p-channel JFET:
In the p-channel JFET, the channel is made up of p-type semiconductor material and two small n-type regions are formed near the channel.
In this video, the construction and working of JFET are explained by taking the example of n-channel JFET. And at the latter part of the video, the output characteristics (Drain curves) and the different region of operation of JFET is also discussed.
Different regions of operation of JFET:
1) Ohmic region
2) Saturation Region
3) Cut-off Region
4) Breakdown Region
This video will be helpful to all students of science and engineering in understanding the construction and working of JFET.
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#JFETWorking
#NchannelJFET
#PchannelJFET
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The timestamps for the different topics covered in the video:
1:01 Construction of n-channel JFET
2:25 Working of n-channel JFET
6:01 Output characteristics (Drain curves) of n-channel JFET
11:07 Different regions of operation of JFET
13:07 p-channel JFET
14:44 Symbols of n-channel and p-channel JFET
Nice explanation in video as well as sequential informed in comment as well ....Thank u...😇😇👍
Please give short note in page so we can study easily
Give notes it may be good
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Me too
Did you pass in the exam
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your lectures are so good,easy to understand,covers all the basics concepts as well as important points that i doubt one could find a better channel for electronics than this. i always feel like I'm in class while watching your lectures. Thanks a lot sir !
this is one of , if not the clearest explaination of a jfet i've come across
nice video!!!
at pinch off voltage, 2 depletion region nearly touch each other, but don't touch it due to electro-static repulsion...
This channel gives the crct explanation on all the theories and concpets...gives much clarity on the subject..tq for this channel members...available the more and more videos on differnet concepts with different expalnations
amazing lecture. even better than my prof at IITM
Ohh!
Really?
Sir No words for you .... You are great... Thanks a lot... It helped me to understand my project related to JFET.
I used it in my circuits on my channel. Thank you for sharing!
Dhanyawad sir bhut accha padhaya apne
The way of explaination is awesome sir👍
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You have helped me a lot for electronics. Thank you so much.
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Great explanation. Cleared my doubts. 🙏
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Clear explanation
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Best explanation!!Thank you very much sir
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excellent explanation makes the topic clear ..
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Keep uploading more videos regarding Electronics..
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Very nice and cool explanation.
I would personally suggest that this is the bestest video on youtube for explaining the concept of JFET.....really impressed brohh...
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Very good explanation ❤
Clear explanation tnk u
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谢谢,很好的解释!
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Nice useful for ...E.E.T..students
Excellent explain sir .
I'm first year ece 2021 corona batch
So classes are running online I didn't understand online classes so I'm came here
thanks you are awesome
good explanation thank you
Tq you giving an information for the jfet.
Thank you so much!
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Love you!
thanks a lotttt, make sense :3
Awesome explain👍
very clear explanation
Best video ever for next day exam 😅
Thank you sir 😊
I have my sem exam tomorrow and i am learning now
thanks a lot!
Super explanation sir
What software do you use to design these circuits? Thanks
Thank you so much
Thanks to indian teacher who made these soo simple
Sir , there is a confusion for me , please be kind enough to see the Motorola data sheet for BFW 10 JFET . Are the pin outs labeled correctly? (Pin 2 with the arrow head is labeled as drain). Your reply is much appreciated.
Thank you so much sir
Great sir thanks a lot
Nice explanation sir
Amazing lecture better than MIT
JFET video is very useful
@12:10 You had put that when Vgs is greater than or equal to Vp the device has 0 drain current. I think you had meant to type when Vgs is less than or equal to Vp, the device has 0 drain current and is in the cut off region
Really Amazing video but please also provide notes it would be really helpful for students
Thank you sir
Thank you.....
Tomorrow is my semester sir thank you 😅
Simple, complete narration of topic.
I am a Master degree student.
What happened if one reversed the polarity of V (ds)?
In some JFET, drain and source terminals are symmetrical. So, if you interchange them it will work fine. (only the direction of current changes accordingly). But it's not allowed in all JFETs I think. Theoretically, it should work fine.
You are copied from neso academy
i usually love your videos but i feel that different widths of depletion region, starting at 4:25, could have been explained better.
Clear 🎉🎉👍👍
Vry great sir
waah maza aa gaya
bas marks aane chahiye
can we interchange source and drain terminals?? if changed what happens.
what if we +ve supply VGS for n channel instead of -ve supply. Will current increase??
While working of n channel,,u r telling reverse saturation voltage increases then depletion region increases. But in bjt explanation, told depletion region decreases. Plz give me clarification
sir make videos on analog and digital communication,
🤩🤩🤩
Nice sir
can you please tell me which software you have used to write all these things. Also, the type of the stylus pen and the writing pad you have used. Please tell me. I want to buy for my research purpose..
You can do this using adobe illustrator, or simply ms paint. apple pen will be the best to go with
The tap-water analogy is a little confusing because you have the flow in reverse in comparison to the FET.
But you can still think of a water-analogy:
Imagine you sitting in your bathtub, and you have a lever (gate) that controls if the water should be drained. When you
pull the lever, the water starts going into the drain, and somewhere down the pipe there will be the "source" where it flows out again, into the canalization.
Of course, if we choose to think of physically-correct current instead of conventional current, then the tap-analogy in this video is correct.
sir you've talked wrong about cutoff voltage, you have said both pinch off and this are same, which is not....
but cant understand the current direction through gate side at the end for both p and n type jfets
So JFETs (both N-Channel and P-Channel) are depletion mode only, allowing current to pass when Vgs = 0
For N-channel (negative Vgs = -Vp , will turn current off)
Explain the working of p channel jfet with neat circuit diagram with cases..?
Yes plz
God bless
U said arrow indicates the direction of flow of current when pn junction is forward biased but actually it is reversed biased right? Then only depletion region is widened.
sir, should
the DEPLETION region in the "p" channel
should be opposite of the "n" channel?
(in case of shape?)
I have a doubt if the pn junction in it is reverse biased then the depletion region decreases and it increases the width of channel present between, so the current Id must rise but it decreases as the gate is made more and more negative and the width is increased....???? So...
Its other way around actually. In pn junction, as the reverse bias increases, the width of the depletion region increases.
Thankyou
When Vds is more than pinch off voltage Vp then both the depletion regions touch each other so the current flow is minimum so why is it itself the maximum current through it?
The thing is, when the Vds is less, then fewer electrons are pumped into the channel (Considering n -channel). As, Vds increases, more electrons are injected into the channel. That means as we increase the voltage Vds, the current increases. But it can happen only up to pinch-off voltage. After that, the drain current gets saturated. So, that's the maximum current.
I hope it will clear your doubt.
SCR video plzz
At 9:52 I don't understand if Vgs is positive or negative at the gate :// and also it's not clear how Vgs is connected looking at the wires. Thanks.
Sir in case of n channel fet how the on junction become reverse bised on application of voltage across drain and source
When Vgs = 0, the gate is at ground potential. Now, when the positive voltage Vds is applied, then the top portion of the n-channel is biased with a more positive voltage. while the p-type region near the gate is still at ground potential.
That's why PN junction is reverse biased. And as I have shown at 5:09, as we move towards the bottom, due to the voltage drop, the PN junction will be less reverse biased. But still, it remains reverse biased.
I hope it will clear your doubt.
i am not clear about the Idss part, why will it be maximum and not ZERO at pinchoff? plz help here
As I mentioned at 8:00, at pinch-off if Id is zero, then the different potential levels which were developed across the channel will be removed. If it is removed then the reverse bias across the pn junction will be removed and if three is no reverse bias then there is no-pinch-off. I mean pinch-off condition would not occur. that's why Id won't be zero.
I hope it will clear your doubt.
@@ALLABOUTELECTRONICS thank you sir, it surely cleared my doubt
Can u make video on SCR( silicon control rectifier )
Soon, will make the video on it.