Yung Tao, age 85, of San Diego, CA, passed away on Saturday, February 16, 2013. He was born on August 14, 1927 in Kunming, China and immigrated to the United States in September 1947 to attend college. He received a B.A. in Political Science from Iowa Wesleyan College before focusing on glass and ceramic engineering at Alfred University in Alfred, NY, where he earned a B.S. in Glass Technology and an M.S. in Ceramic Engineering. While at Alfred, he met his wife Grace and they married on September 5, 1953. After initial jobs at North American Refractories, Sylvania Electric and Westinghouse Electric, he went on to work at Texas Instruments in Dallas Texas. There, as Manager and Chief Product Engineer of hermetic seals and header development, he was instrumental in developing technologies needed to produce the first integrated circuit assemblies. In 1971 he and his family moved to San Diego, CA, where he became Vice President of Dielectric Systems and subsequently, a founding partner of Ceramic Systems, where he served as Vice President and later President. At these companies, Yung developed important new technologies for the rapidly advancing semiconductor industry. He spent the final few years of his career at Amdahl Corp., where he was involved in the design and development of mainframe computers. In addition to his professional career, Yung also built a successful side business around the Southern California real estate boom. After retirement, he became a Certified Financial Planner and worked in that field for a short time. Yung was the patriarch of the extended family and worked ceaselessly to bring the family together and provide for everyone's futures. As well as providing for his immediate family, he sponsored his nieces Mindy and Jing and their families, plus four other Chinese students into the United States, and helped them all become established. In his later years he lived a quiet life tending his koi pond at his home in University City. In the end he was content with what he had achieved in his life and was at peace, knowing that he was leaving his family whole and well. He is survived by his wife Grace, daughter Janet (Mike Rapozo), sons Andy (Jeanne Beesley) and Peter (Jenny Chen) and granddaughter Aimee. He is sorely missed by all.
I worked with a Tung Tao in the late 70’s at a company in San Diego called Ceramic Systems. He was an older engineer there and was a very nice guy. I had no idea until I watched the video that he was the inventor of a type of semi package at TI.
11:07 Note that the pins of the chip shown here are not gull-wing, they are J-leads, which are designed to be both solderable and socketable. In fact if you look at the pin that's in focus, you can see the vertical scratches from this chip previously being in a socket.
@@Asianometry This kind of package is called a SOJ rather than SOIC. The more common four-sided version is PLCC (used for CPUs, FPUs or ROM chips for some time before they either switched to SMT or PGA)
There's a few other places where images don't really line up with what's being talked about I think... but then I suppose this is a video about the history, not technical details of each packaging.
9:01 I'd also add, that it's not just "drilling a hole" through the PCB. That would be the least of it. The hole needs to be electrically conductive and solder must adhere to it perfectly. The most usual way to do it is to deposit copper chemically.
I think that advancements of PCB technology deserve an entire video on its own. The minimum size of vias, trace width and clearance is nowadays more of a limitation than the size of the components.
I'd argue the number of holes drilled is a cost driver. You can only drill 1 hole at a time, but whether the board has 1 or 100 through holes it will essentially take the same time to electroplate. On the other hand, boards will still often be "peppered with holes" because even without through hole chips, you need vias. All of this is of course context dependent, what the board was used for and which time period we're talking about. For example, in the early days it would have been much more common with single sided boards, which did not have through plated holes.
Here's the conspiracy theory as to why he added that note. As Nara deer himself, he's tired of the prejudiced view that the deer in Nara region like to bump into people to make them drop food on the ground that they can steal. So he's trying to shift the focus to seagulls instead... Did I btw mention that most Nara deer are law-abiding citizens, who are even known to wait by red lights before crossing the road?
Through hole dip lead spacing was in 0.1 inch increments. So tenths of an inch was the standard grid we designed our circuit boards with. That went out the window when working with surface mount components. Then sizes and spacing were not based on division by 10 of either metric or imperial. While there are standard lead pitches for surface mount it wasn't based on a standard unit of measure. Basically we used mils as the base unit for a design (1000 mill = 1 inch) and not designed with inches. Sometimes I would use metric as the base. It really depends on how you would be interfacing to external parts. When I started designing circuit boards we did it on a light table that had a 1/10th inch grid. We used black stick on dots for pads on the sheet of mylar . Translucent red tape would be used to make the traces for the top sheet, for the top of the board. Blue tape to make the traces on the bottom of the sheet for the traces on the bottom of the board. When done the artwork was photographed with filters to separate the red and blue sides (top and bottom) At about 1985 we started to design on computer.
I'm biased because it's my field but I'd love to see your take on the field of modern Signal Integrity - packaging advancements such as what you've described here have been crucial to allowing us to make electrons dance in just the right way. Thanks for the video!
Anecdotal of course, but It seems to me like people began to notice that those who worked with the chemicals to fabricate printed circuit boards such as freon and those who worked with arsenic, phosphorus and boron to dope the n and p type junctions in semiconductors began to die horribly in the mid 1970s and that semiconductor manufacturing left "silicon valley" for taiwan and malaysia shortly thereafter.
Hello Jon, I am a Senior in highschool beginning my journey into EE, and your videos are a great way to learn about the EE industry as a whole, I like to say its all about learning to stand on the shoulders of giants, and your channels is the best way to learn for that. Thank you for your videos, I really appreciate them.
This is a fairly good list of the variety of package types for digital ICs. It seriously misrepresents the actors and difficulties of plastic packages. For example it’s not gooping plastic around a chip, it’s high speed injection molding. There is still a problem with bond wires touching during the molding process, and there’s a complex program to verify that a given pad arrangement on the chip works with a given lead frame and package design. The plastic is generally injected from below the chip to make the bond wires go upward. This seems obvious now, but I have talked to someone who was around at the time, and he said it was not obvious then. He worked at Texas Instruments, not at Fairchild, and I believe TI had the patent for that and did lots of other crucial work on plastic packaging. Another issue on plastic packaging is stress on the chip. There is residual stress on the chip because the plastic equilibrium warp a bit as it cools after the injection. The stress will change with soldering and with temperature changes during operation. This isn’t too bad for purely digital chips, but if you’re trying for good analog performance, need to design for it. Ceramic packaging is much more stable. Normally testing is done on the wafer as well, not just after packaging. That way the packaging cost is avoided for most of the defective devices. There are lots of interesting packages not mentioned for chips which require high analog performance, high power dissipation, or high voltage - 1500 V is common - isolation.
Thank you for sharing. I think Asianometry must have had to make a lot of hard edits in his script. I don't think he intentionally misrepresented plastic packaging. it's the CZcams game at play or just a lack of time to get the script worked out just right. Since this was just a primer for variety of packaging types I am sure he could go into in-depth detail if there is enough interest.
an interesting sideline in chip packaging was the alpha-particle contamination issue affecting early dynamic ram chips in ceramic packages -- in some ceramic packages, the ceramics contained alpha emitters, which introduced errors into the DRAM cells... when this was discovered, the hunt was on for alpha-free packaging. One winner, Coors Ceramics.
Another great video! Love your work man - it's like small lectures with just right amount of infortmation for one go. They're structured great, occasional small jokes, and no other unnecessary jibber-jabber. Very nice! By the way, you're focusing on quite niche subjects that are becoming more and more mainstream - props for that! Keep up the good work!
thanks for this video! I'm taking a MEMS design course this semester (inspired by your earlier videos) and this packaging video released right around the same time as our chapter on packaging... great overview!
@4:56 it seems you are referring to the 'black blobs' (no lead frame) found inside many cheap (toy) electronics. Yet the pictures do show something very different (DIP with leadframes)
When I worked at Nortel I was told by a colleague who had two PhDs and two masters degrees that if you ever want to make infinite money specialize in packaging
I think your editing and content is perfect. To add to your video: 14:04 and C-SAM scanning ultrasonic metrology, 15:24 "Wafer level Board" WLB and "enhanced wafer level board" eWLB ~2009 are interesting because they exploited both existing PCB and wafer manufacturing equipment. The eWLB reassembles the cut die chips into a "plastic" wafer that can continue to process the chips as a wafer, even though more than 50%wafer is plastic.
IBM's version of the ball grid array dates to the 1960's. A patent for the solder ball started it all. The use of resist allowed an array to be registered with the flip chip - face down IC. The image shown here includes the addition of the pins to that array in a ceramic package. All of this was available by the early 1970's and was held inisde the company by patents. When patents expired others tried to duplicate, but the learning curve kept it inside IBM for another decade.
THANK YOU!!! I've had packaging on my mind recently... even since learning about the MI300 from AMD... SO I am SUPER STOKED about you covering 3D packaging (hopefully)soon :D
Another intersting thing about packaging is that if you were to package a MEMs that require some sort of open to the outer world to enable them to function properly (such as hydrophone), now you're in a situation trying to balance between enclosing the chip for better protection and fully open the part in qusetion to enable best sencing performance. In the end the packaging design is thought of during the IC design stage, ensuring the circuit layout is easy to work with, meanwhile definign the package to cope with the IC and make sure the performance satisfy the target usage critiria. The balance sure is delicate, most of the time they will require specialized packaging method, equipment and material.
Thank you so much for making this video! Just came across your channel through this video today, and I must say it is really useful to get an understanding of many things semiconductor!
I like the format of following a technology through various companies rather than following a company through various technologies. Nice change of pace.
Semiconductor packaging has always been fascinating to me. My joy at the arrival of this video on my landing page was palpable. Please do Trash Pyrolysis next (I think Japan is big into this).
I'm an old timer, and when I got into the business, the DIP was king. A lot of TO-5 (actually TO-99) still used for analog chips. 40-pins was really the practical limit for the DIP, though some were made with more pins. I have a 64-pin DIP 68000 displayed on my desk. Surface mount components were heavily used on ceramic hybrids, long before becoming common on PCBs. I believe surface mount sales only passed thru-hole, in the early to mid 1990s.
Amazing. Great explanation and overview. You did a great job. If I would teach in a university a related subject I would use your video as an introduction and background.
Nice summary of packaging. It might be also interesting to compare it in parallel to how chips, CPUs, RAMs, or system parts could be interchanges with slots, PGA, LGA, etc.
There are couple of mistakes, but in general this is good material for most microelectronic students .) THT (through hole tech) can of course use both sides of boards either only THT/THT or more frequently as combination of THT+SMD. SMD boards of course have plenty of holes, in fact even more than THT, but mostly used as via and masked. SMD technology was enabled by SOLDER PASTE and REFLOW soldering. It was never meant to be manually soldered. And the economical side is not on reducing number of holes but on SIZE reduction. PCB cost per square area and number of layers. But if you are able to squeeze much more components on smaller place and run the whole pannel through printer and oven as one cycle, you are saving money on increased density. PGA was nice, but it was not only about number of leads, but about possibility of insert chip into socket and replace if needed. BGA does not offer such option.. But have much higher density. CSP/WLP brought 3D stacking in large amount of structures. And you can add how even PCB itself can be used for stacking layers of burried components..
I don't even work on this industry to be so interested on the topic. But the way you present your videos is so pleasurable that I watch as I would any good TV show.
Thanks for the nice overview of the packaging topics! After watching the video, I realized that most of the "traditional" packaging techniques like DIP, SMT, BGA were developed and commercialized quickly in 1980s and 1990s. But it took another 20 years for the advance packaging to develop and really get into broader industry use. Is it because these advance packaging won't offer as much of the improvements or what else is impeding a quicker evolution on silicon packaging?
I'm currently thinking about making an PhD in the field of Semiconductors and your Videos deliver so much fascination and in depth views so I really want to thank you for your work. I hope I'll have half of your knowledge one day.
14:28 it is my understanding of the nomenclature is that bumps are on the silicon and balls are on the BGA, so the interposer has pads on the top for the bumped die and balls on the bottom for the PCB. Of course you can now just get bumped die as a CSP from the manufacturer, considerably saving space at the cost of more complex PCB routing (since there is no longer an interposer between the chip and the PCB). These are usually low pin count devices for this reason.
Just out of high school in the late 70's I got a job at a company as the shipping and receiving clerk. They made LASER markers but they also did stuff with PCB stuff with IC's and such. I remember some boards going to Sandia National labs. Anyway I remember twice I did some dumb things. One was removing a IC chip test probe with all the fine needle like array and see how ridgid they were from there mount making sure not the move them from position having no idea how fine their position was. The other time I had a Galvo servo motor that rotated (a mirror) the laser light in a plane, 2 working together to etch. I was curious about the shafts motion and rotated it to full stop both ways. I do not think it was made to do that after afew years thinking back.
Great concise video. There's a whole world of content just on the first step, wafer dicing. Sawing, laser ablation, plasma, etc. The chosen method will directly affect die density, yield and robustness as well as the amount of investment you need to make. Like the style of the videos though, they are good to recomend to our new employees as background viewing in their early days.
Good point. Also don't forget the wafer bumping process prior to dicing, but subsequent to wafer fabrication. And then there is burn-in at the conclusion of the back end. Jon's only limitation is his ability to burn the candle on both ends as he produces these videos in his "spare time".
13:39 Interestingly, IBM was actually selling metal can PGA chips as well, mostly for internal use. I believe they saw use primarily for ASICs, and the only times I've seen them in person are on the IBM 8514A video card and the PCBs of several of their Rochester designed voice coil hard drives of the early and mid 80s, like the 0665-53.
This of course is also just for signal level packaging. As a power electronics guy I can tell you packaging power devices is a huge field of study right now. You can imagine the advantages of halving the size of a motor drive in an EV or doubling the power handling of a device with improved cooling as a result of packaging. I also see PCBA line operators and rework and service technicians curse the day BGA was conceived on a regular basis, and I cant say I'm not sympathetic.
"the wire bonding got more advanced, it's beyond the scale of the video but you should know it exist" The number of video that doesn't admit that, and I was just looking this up, good video
Minor adjustment, there's no need for d-i-p. It's pronounced dip, rhymes with tip or nip. The single-inline is SIP, pronounced sip. Detail, through holes are not about structural integrity at all, just making connections between pins.
Just looking at the intermittent operation of the VU meters of a 1984 Sony Beta Hifi video recorder. Glob-top chip packaging failure. Glob-top makes for very high package density at the expense of serviceability and possibly reliability, but is used extensively in consumer products.
I agree with your 'chopped liver' 🙂assessment, but I'd loved to see a list with few main reasons (i.e. enabling technologies food chain), what's the market worth or who are the key players. Great info, unique content, thanks!
IBM was one of the first users of the flip chip ball attach method. While expensive it not only increased signal performance but exposed the back side of the die to attach to a heat sink.
An early (c. early 1960's) version of the ball grid array was IBM's original C4 (Controlled Collapse Chip Connection). Individual transistors, and later, ICs, were mounted on ceramic substrates that had arrays of pins to attach to the circuit boards. This technology was introduced with S/360 (c. April 1964).
Bond wires don’t connect lead frames “to the the outside world.” Quite the opposite: They connect them to the encapsulated die. The leads themselves are what connect to the outside world. Also, when you introduce DIP you begin by describing thru-hole tech (THT) as if that distinguishes it from TO-5... though obviously TO-5 was THT as well. You describe SIP/DIP as being 12-16 pins at first while showing 8 and 9 pin packages.
I had work in Texas Instruments semiconductor packaging before. This is a number intensive job. All they care are numbers of chips per day output. All the chips made then store inside the warehouse waiting to ship out to customers in waiting. Sometimes they would purposely ram up production not to ship out but to keep as surplus stock. Once the target numbers achieved, they would declare mass unpaid vacation to all the production workers.
On the other end TI won a LOT of business by being cut throat in its pricing. The FAA contract for the American inter route computer around 1967 say. Sylvania chips were faster.
Nice video, just one thing... At 11:10 you're not showing gullwing style pins, but J shape... those are made to be socketed or soldered and were sometimes seen socketed on fancier motherboard as BIOS chips. Those boards often came with a second spare backup chip. Basically the predecessor of dual BIOS.
About recent adoption of TSVs, they are an absolute nightmare for the back-end engineers. Being a floorplanner, seing a nice rectangular die being punctured with 20000 no use holes is still the stuff of nightmares, even after taping out 2 chips with TSVs. Random timing fails never on connections before seen in previous chips requiring changes to RTL to increase latency.. power grids having to do a jiggle around holes and sometimes introduces crosstalk to low voltage sectors.. and the tools being absolutely unprepared for these kind of situations.
I was watching DankPods recently, and he opened a knock-off handheld game where they didn't even package the microchip. it's just glued to the board all exposed. And I don't mean they covered it in glue, it's just held on with a drop underneath it. I still can't get over that horror lol.
Wonder how many college syllabuses refer to this channel. I bet there's a lot of them. Unmatched coverage of the history of the industry and all around good work.
Probably none, EE degrees don't really cover that stuff (I think they should a bit) but also these videos are not quite accurate enough for someone looking to work in the industry to use as a reference.
Great video on the history of packaging. What I don't understand and amaze me is how they can connect 2000+ leads from a chip to the outside world, are they still connecting to the edge of the IC with some bound wires or welding the chip to the packacge and at what kind of pitch density, how many layers are built into a carrier. What can be the cost of the package on a 2000+ pins CPU? I'm looking forward for your next videos.
As I understood, chip is soldered directly to the package. It's being made itself like a BGA at first, then flipped upside down and have its balls solfered to the inside ends of the pins of the package.
In flip-chip, BGA, or PGA, is the die connected through to the packaging via solder balls instead of bond wires then? I'd love to see a picture of the back of these things; the connection side, with the die and the connection to the packaging visible. Is it really possible to just glue a ball of metal to a silicon die like that? Fascinating.
Actually he mentioned that but the picture shown was not for that technology. I can't be sure if it was a misunderstanding on his part or maybe a mixup in the production of the video. On the whole he does a good job.
Interposer don't have to be silicon, and is worth mention, because TSMC is using not silicon version a lot in finout design, cheaper, smaller, lighter. And is use in eg AMD Radeon RX 7900 XT/XTX to connect external memory controllers with cache. There are leaks that saying this are made so cache can be stuck on them (as 3d v-cache in Ryzen 5800X3D). And many with organic substrate are used in phones eg Apple using them for many years (chip on chip, when bottom is connect to interposer which is bigger and added connection to top chip around... weird but heat is [I think] main reason what is on top).
Super interesting as always! Question though (maybe I missed a comment): is it not "lead frame" as in the metal and not lead as in "leading"? Although that sounds a bit weird since the leads are connected to it... Although, I'm being told they are called leads as in the metal?? Hold on, what the h...?
Hi, I got a question! You mentioned putting the PCB board in an oven thingy as a way to solder everything in one go but, how can you melt the lead with enough heat without destroying the delicate IC?
Yes. As you point out it is a difficult problem. It is handled by controlling the rates of temperature rise/fall. Peak temperature and dwell time at peak temperature. Moisture content must also be controlled.
16:40 - package on package is a pain in the neck to do signal analysis / reverse-engineering inter-package communication . The techniques to interpose are currently risky and expensive to undertake, how I do miss DIP packaging so.
small correction, the chip shown at 11:08 is not a SOP, it is a SOJ - small outline j-lead package. It's main characteristic is that the pins are in the shape of the "J" letter and curve in under the chip. They use less area but they are taller than normal SOP chips. There's also a quad version known as PLCC which I loathe with a passion. I suspect their main advantage over gull wings is that they can be socketed rather effortlessly, there used to be PC expansion cards that used SOJ sockets for memory expansions, but I've also seen a BIOS chips using PLCC sockets.
Yung Tao, age 85, of San Diego, CA, passed away on Saturday, February 16, 2013. He was born on August 14, 1927 in Kunming, China and immigrated to the United States in September 1947 to attend college. He received a B.A. in Political Science from Iowa Wesleyan College before focusing on glass and ceramic engineering at Alfred University in Alfred, NY, where he earned a B.S. in Glass Technology and an M.S. in Ceramic Engineering. While at Alfred, he met his wife Grace and they married on September 5, 1953. After initial jobs at North American Refractories, Sylvania Electric and Westinghouse Electric, he went on to work at Texas Instruments in Dallas Texas. There, as Manager and Chief Product Engineer of hermetic seals and header development, he was instrumental in developing technologies needed to produce the first integrated circuit assemblies. In 1971 he and his family moved to San Diego, CA, where he became Vice President of Dielectric Systems and subsequently, a founding partner of Ceramic Systems, where he served as Vice President and later President. At these companies, Yung developed important new technologies for the rapidly advancing semiconductor industry. He spent the final few years of his career at Amdahl Corp., where he was involved in the design and development of mainframe computers. In addition to his professional career, Yung also built a successful side business around the Southern California real estate boom. After retirement, he became a Certified Financial Planner and worked in that field for a short time. Yung was the patriarch of the extended family and worked ceaselessly to bring the family together and provide for everyone's futures. As well as providing for his immediate family, he sponsored his nieces Mindy and Jing and their families, plus four other Chinese students into the United States, and helped them all become established. In his later years he lived a quiet life tending his koi pond at his home in University City. In the end he was content with what he had achieved in his life and was at peace, knowing that he was leaving his family whole and well. He is survived by his wife Grace, daughter Janet (Mike Rapozo), sons Andy (Jeanne Beesley) and Peter (Jenny Chen) and granddaughter Aimee. He is sorely missed by all.
Much appreciated !
RIP, making circuits in the sky. ❤
As someone doing their PhD in advanced packaging, I'm glad it's being discussed 😊 can't wait for the 3DHI video
That's absolutely awesome! You're working in an exciting field! Have you published anything yet? :D
Don't you know, by chance, why AMD still using PGA, while Intel using LGA mounts?
Good luck!👍
@@nanonymous9139 amd ditched pga on their lates cpu
@@taktuscat4250 still, why only now?
I worked with a Tung Tao in the late 70’s at a company in San Diego called Ceramic Systems. He was an older engineer there and was a very nice guy. I had no idea until I watched the video that he was the inventor of a type of semi package at TI.
Larry Harmon was the lead inventor.. and it's Yung Tao, not Tung: different surname.
11:07 Note that the pins of the chip shown here are not gull-wing, they are J-leads, which are designed to be both solderable and socketable. In fact if you look at the pin that's in focus, you can see the vertical scratches from this chip previously being in a socket.
My bad.
@@Asianometry At the current rate of development, how long will it take for china to design and mass-produce advanced chips?
@@prasanth2601 depends if the rest of the world lets china get access to EUV lithography as currently noone is willing to sell the tech to them
@@Asianometry This kind of package is called a SOJ rather than SOIC. The more common four-sided version is PLCC (used for CPUs, FPUs or ROM chips for some time before they either switched to SMT or PGA)
There's a few other places where images don't really line up with what's being talked about I think... but then I suppose this is a video about the history, not technical details of each packaging.
9:01 I'd also add, that it's not just "drilling a hole" through the PCB. That would be the least of it. The hole needs to be electrically conductive and solder must adhere to it perfectly. The most usual way to do it is to deposit copper chemically.
I think that advancements of PCB technology deserve an entire video on its own. The minimum size of vias, trace width and clearance is nowadays more of a limitation than the size of the components.
I'd argue the number of holes drilled is a cost driver. You can only drill 1 hole at a time, but whether the board has 1 or 100 through holes it will essentially take the same time to electroplate. On the other hand, boards will still often be "peppered with holes" because even without through hole chips, you need vias. All of this is of course context dependent, what the board was used for and which time period we're talking about. For example, in the early days it would have been much more common with single sided boards, which did not have through plated holes.
I made a lot of boards without that though.
Ya, a whole laser industry is built around "drilling" those holes. A video on MKS instruments and advanced small PCB boards would be great.
Good video. I'm particularly pleased that you cleared up the confusion about seagulls.
His comedic editing skill is incredible. The meme is so small it's like a footnote. I can't get over it.
They steal chips too (the potato kind, not the silicon kind).
@@adissentingopinion848
M
Here's the conspiracy theory as to why he added that note. As Nara deer himself, he's tired of the prejudiced view that the deer in Nara region like to bump into people to make them drop food on the ground that they can steal. So he's trying to shift the focus to seagulls instead... Did I btw mention that most Nara deer are law-abiding citizens, who are even known to wait by red lights before crossing the road?
Thank you for treating the inch with the respect it deserves.
Respect where respect is due. At least 3 devoloping countries are still using this standard.... Unbelievable 🤣
more like unbelievably based
Through hole dip lead spacing was in 0.1 inch increments. So tenths of an inch was the standard grid we designed our circuit boards with.
That went out the window when working with surface mount components. Then sizes and spacing were not based on division by 10 of either metric or imperial. While there are standard lead pitches for surface mount it wasn't based on a standard unit of measure.
Basically we used mils as the base unit for a design (1000 mill = 1 inch) and not designed with inches. Sometimes I would use metric as the base. It really depends on how you would be interfacing to external parts.
When I started designing circuit boards we did it on a light table that had a 1/10th inch grid. We used black stick on dots for pads on the sheet of mylar . Translucent red tape would be used to make the traces for the top sheet, for the top of the board. Blue tape to make the traces on the bottom of the sheet for the traces on the bottom of the board. When done the artwork was photographed with filters to separate the red and blue sides (top and bottom) At about 1985 we started to design on computer.
@@illeatmyhat I think you mean, 'damned with faint praise'.
You are about "...shrinked down to 0.65 mm. Calculate many inches it is by yourself"?
I'm biased because it's my field but I'd love to see your take on the field of modern Signal Integrity - packaging advancements such as what you've described here have been crucial to allowing us to make electrons dance in just the right way. Thanks for the video!
I'm biased because I'd love to see you dance in just the right way.
Was thinking the same thing.
@@TimPerfetto lmao touche; don't know what I expected >_>
I would love to see a video on the transition of semiconductor manufacturing from Europe and America to largely Asia.
Anecdotal of course, but It seems to me like people began to notice that those who worked with the chemicals to fabricate printed circuit boards such as freon and those who worked with arsenic, phosphorus and boron to dope the n and p type junctions in semiconductors began to die horribly in the mid 1970s and that semiconductor manufacturing left "silicon valley" for taiwan and malaysia shortly thereafter.
@@seanm8030 as well as an increase in miscarriages and the cleanup of former fab locations.
@@tygerbyrn I was there at the time but was not paying attention so to speak, so I cannot really confirm or deny, other than not myself being dead.
@@seanm8030 Me too at NSC in Connecticut
@@johnforguites4800 I liked national's ads with Widlar. Digital? Because any idiot can count to 1.
Hello Jon, I am a Senior in highschool beginning my journey into EE, and your videos are a great way to learn about the EE industry as a whole, I like to say its all about learning to stand on the shoulders of giants, and your channels is the best way to learn for that. Thank you for your videos, I really appreciate them.
This is a fairly good list of the variety of package types for digital ICs. It seriously misrepresents the actors and difficulties of plastic packages. For example it’s not gooping plastic around a chip, it’s high speed injection molding. There is still a problem with bond wires touching during the molding process, and there’s a complex program to verify that a given pad arrangement on the chip works with a given lead frame and package design. The plastic is generally injected from below the chip to make the bond wires go upward. This seems obvious now, but I have talked to someone who was around at the time, and he said it was not obvious then. He worked at Texas Instruments, not at Fairchild, and I believe TI had the patent for that and did lots of other crucial work on plastic packaging. Another issue on plastic packaging is stress on the chip. There is residual stress on the chip because the plastic equilibrium warp a bit as it cools after the injection. The stress will change with soldering and with temperature changes during operation. This isn’t too bad for purely digital chips, but if you’re trying for good analog performance, need to design for it. Ceramic packaging is much more stable.
Normally testing is done on the wafer as well, not just after packaging. That way the packaging cost is avoided for most of the defective devices.
There are lots of interesting packages not mentioned for chips which require high analog performance, high power dissipation, or high voltage - 1500 V is common - isolation.
Thank you for sharing.
I think Asianometry must have had to make a lot of hard edits in his script. I don't think he intentionally misrepresented plastic packaging. it's the CZcams game at play or just a lack of time to get the script worked out just right. Since this was just a primer for variety of packaging types I am sure he could go into in-depth detail if there is enough interest.
He does say that epoxy'ing or plastic packaging can still be prone to failure...
an interesting sideline in chip packaging was the alpha-particle contamination issue affecting early dynamic ram chips in ceramic packages -- in some ceramic packages, the ceramics contained alpha emitters, which introduced errors into the DRAM cells... when this was discovered, the hunt was on for alpha-free packaging. One winner, Coors Ceramics.
And some small credit to Intel for sharing this discovery, after they had mitigated it.
I've been waiting for this one! Thanks for illuminating that murky, physical space between chip design and circuit design 🙏
In my career, I've always heard the DIP package pronounced as the word dip and not as the letters D, I and P. Great video. Appreciate your work!
Nice video. The device shown at 3:24 is not an IC as such, it is a hybrid circuit packaged like an IC.
Another great video!
Love your work man - it's like small lectures with just right amount of infortmation for one go. They're structured great, occasional small jokes, and no other unnecessary jibber-jabber. Very nice!
By the way, you're focusing on quite niche subjects that are becoming more and more mainstream - props for that! Keep up the good work!
thanks for this video! I'm taking a MEMS design course this semester (inspired by your earlier videos) and this packaging video released right around the same time as our chapter on packaging... great overview!
@4:56 it seems you are referring to the 'black blobs' (no lead frame) found inside many cheap (toy) electronics. Yet the pictures do show something very different (DIP with leadframes)
That's called "chip on board" by the way.
The PCB tech had to keep up, Signal Integrity replaces Timing analysis.
I (used to) teach a class on IC packaging, and I have to say this video is very well done. Good job!
When I worked at Nortel I was told by a colleague who had two PhDs and two masters degrees that if you ever want to make infinite money specialize in packaging
Is it chemistry
You deserve so many more subscribers, truly fantastic content.
I think your editing and content is perfect. To add to your video: 14:04 and C-SAM scanning ultrasonic metrology, 15:24 "Wafer level Board" WLB and "enhanced wafer level board" eWLB ~2009 are interesting because they exploited both existing PCB and wafer manufacturing equipment. The eWLB reassembles the cut die chips into a "plastic" wafer that can continue to process the chips as a wafer, even though more than 50%wafer is plastic.
IBM's version of the ball grid array dates to the 1960's. A patent for the solder ball started it all. The use of resist allowed an array to be registered with the flip chip - face down IC. The image shown here includes the addition of the pins to that array in a ceramic package. All of this was available by the early 1970's and was held inisde the company by patents. When patents expired others tried to duplicate, but the learning curve kept it inside IBM for another decade.
THANK YOU!!! I've had packaging on my mind recently... even since learning about the MI300 from AMD... SO I am SUPER STOKED about you covering 3D packaging (hopefully)soon :D
I love the small bits of humor in your videos it makes it much more enjoyable
I have waited for this video for so long! Thank you!
Really enjoy your style. You strike the right balance. You manage to be informative without being tedious. Thanks for sharing!
“mine mine mine!” - seagulls
Another intersting thing about packaging is that if you were to package a MEMs that require some sort of open to the outer world to enable them to function properly (such as hydrophone), now you're in a situation trying to balance between enclosing the chip for better protection and fully open the part in qusetion to enable best sencing performance. In the end the packaging design is thought of during the IC design stage, ensuring the circuit layout is easy to work with, meanwhile definign the package to cope with the IC and make sure the performance satisfy the target usage critiria. The balance sure is delicate, most of the time they will require specialized packaging method, equipment and material.
Awesome video. You don't miss. The consistency is why you keep earning my pateron sub every month. Keep it up!
This video is TRULY REMARKABLE ! Thank you for your effort & time !
Excellent video as always! 😊
Thank you so much for making this video! Just came across your channel through this video today, and I must say it is really useful to get an understanding of many things semiconductor!
As always ... Outstanding vlog and information.
I like the format of following a technology through various companies rather than following a company through various technologies. Nice change of pace.
Semiconductor packaging has always been fascinating to me. My joy at the arrival of this video on my landing page was palpable.
Please do Trash Pyrolysis next (I think Japan is big into this).
Love it, keep it on. That's the content that missing from IT education, and it's fascinating.
I'm an old timer, and when I got into the business, the DIP was king. A lot of TO-5 (actually TO-99) still used for analog chips. 40-pins was really the practical limit for the DIP, though some were made with more pins. I have a 64-pin DIP 68000 displayed on my desk. Surface mount components were heavily used on ceramic hybrids, long before becoming common on PCBs. I believe surface mount sales only passed thru-hole, in the early to mid 1990s.
Amazing. Great explanation and overview. You did a great job.
If I would teach in a university a related subject I would use your video as an introduction and background.
I always knew when I was looking at a dip switch, but never knew why it was a dip switch until now.
Amazing video, excellent work!
Thanks for summarising it so well! For someone who uses these packages on a daily basis it's always interesting to see how they came about
Love this info on the packages. Would love another vid on it or more.
Nice summary of packaging. It might be also interesting to compare it in parallel to how chips, CPUs, RAMs, or system parts could be interchanges with slots, PGA, LGA, etc.
There are couple of mistakes, but in general this is good material for most microelectronic students .)
THT (through hole tech) can of course use both sides of boards either only THT/THT or more frequently as combination of THT+SMD.
SMD boards of course have plenty of holes, in fact even more than THT, but mostly used as via and masked. SMD technology was enabled by SOLDER PASTE and REFLOW soldering. It was never meant to be manually soldered. And the economical side is not on reducing number of holes but on SIZE reduction. PCB cost per square area and number of layers. But if you are able to squeeze much more components on smaller place and run the whole pannel through printer and oven as one cycle, you are saving money on increased density.
PGA was nice, but it was not only about number of leads, but about possibility of insert chip into socket and replace if needed. BGA does not offer such option.. But have much higher density.
CSP/WLP brought 3D stacking in large amount of structures.
And you can add how even PCB itself can be used for stacking layers of burried components..
I don't even work on this industry to be so interested on the topic. But the way you present your videos is so pleasurable that I watch as I would any good TV show.
This is great!!!! Good stuffs and so informative!
Thanks for the nice overview of the packaging topics! After watching the video, I realized that most of the "traditional" packaging techniques like DIP, SMT, BGA were developed and commercialized quickly in 1980s and 1990s. But it took another 20 years for the advance packaging to develop and really get into broader industry use. Is it because these advance packaging won't offer as much of the improvements or what else is impeding a quicker evolution on silicon packaging?
I'm currently thinking about making an PhD in the field of Semiconductors and your Videos deliver so much fascination and in depth views so I really want to thank you for your work. I hope I'll have half of your knowledge one day.
14:28 it is my understanding of the nomenclature is that bumps are on the silicon and balls are on the BGA, so the interposer has pads on the top for the bumped die and balls on the bottom for the PCB.
Of course you can now just get bumped die as a CSP from the manufacturer, considerably saving space at the cost of more complex PCB routing (since there is no longer an interposer between the chip and the PCB). These are usually low pin count devices for this reason.
Just out of high school in the late 70's I got a job at a company as the shipping and receiving clerk. They made LASER markers but they also did stuff with PCB stuff with IC's and such. I remember some boards going to Sandia National labs. Anyway I remember twice I did some dumb things. One was removing a IC chip test probe with all the fine needle like array and see how ridgid they were from there mount making sure not the move them from position having no idea how fine their position was. The other time I had a Galvo servo motor that rotated (a mirror) the laser light in a plane, 2 working together to etch. I was curious about the shafts motion and rotated it to full stop both ways. I do not think it was made to do that after afew years thinking back.
Love this guy. Never fails with his videos. A++
I appreciate the quality of these videos
Excellent video! I would have liked to have seen mention of COB (Chip On Board) though, and maybe fully 2D multichip packages
Great concise video.
There's a whole world of content just on the first step, wafer dicing.
Sawing, laser ablation, plasma, etc.
The chosen method will directly affect die density, yield and robustness as well as the amount of investment you need to make.
Like the style of the videos though, they are good to recomend to our new employees as background viewing in their early days.
Good point. Also don't forget the wafer bumping process prior to dicing, but subsequent to wafer fabrication. And then there is burn-in at the conclusion of the back end. Jon's only limitation is his ability to burn the candle on both ends as he produces these videos in his "spare time".
13:39 Interestingly, IBM was actually selling metal can PGA chips as well, mostly for internal use. I believe they saw use primarily for ASICs, and the only times I've seen them in person are on the IBM 8514A video card and the PCBs of several of their Rochester designed voice coil hard drives of the early and mid 80s, like the 0665-53.
JTAG is also up there with packaging miniaturisation
14:06 Reballed and reapplied. Reminds me of college.
Great video. By the way, would love to see a video just on Bell Labs sometime.
11:30 The most important piece of information I gathered from this is that Gull wing isn't gold wing. I never knew. I feel stupid.
This of course is also just for signal level packaging. As a power electronics guy I can tell you packaging power devices is a huge field of study right now. You can imagine the advantages of halving the size of a motor drive in an EV or doubling the power handling of a device with improved cooling as a result of packaging.
I also see PCBA line operators and rework and service technicians curse the day BGA was conceived on a regular basis, and I cant say I'm not sympathetic.
"the wire bonding got more advanced, it's beyond the scale of the video but you should know it exist"
The number of video that doesn't admit that, and I was just looking this up, good video
You know I had no idea about semiconductors and their history before I came across your channel. You have educated me a great deal. Thank you.
DITTO !
Minor adjustment, there's no need for d-i-p. It's pronounced dip, rhymes with tip or nip. The single-inline is SIP, pronounced sip.
Detail, through holes are not about structural integrity at all, just making connections between pins.
Eh, typical for this channel, always some super basic errors…
Great topic, thanks for the video.
This channel is amazing!
My man just gave a 3 credit ENT course in 18 minutes
Just looking at the intermittent operation of the VU meters of a 1984 Sony Beta Hifi video recorder. Glob-top chip packaging failure. Glob-top makes for very high package density at the expense of serviceability and possibly reliability, but is used extensively in consumer products.
I agree with your 'chopped liver' 🙂assessment, but I'd loved to see a list with few main reasons (i.e. enabling technologies food chain), what's the market worth or who are the key players. Great info, unique content, thanks!
Nice work! Would you go beyond each process like wafersort, backgrind, dicing, die attach and wire bonding?
IBM was one of the first users of the flip chip ball attach method. While expensive it not only increased signal performance but exposed the back side of the die to attach to a heat sink.
An early (c. early 1960's) version of the ball grid array was IBM's original C4 (Controlled Collapse Chip Connection). Individual transistors, and later, ICs, were mounted on ceramic substrates that had arrays of pins to attach to the circuit boards. This technology was introduced with S/360 (c. April 1964).
Thanks for sharing
Bond wires don’t connect lead frames “to the the outside world.” Quite the opposite: They connect them to the encapsulated die. The leads themselves are what connect to the outside world.
Also, when you introduce DIP you begin by describing thru-hole tech (THT) as if that distinguishes it from TO-5... though obviously TO-5 was THT as well. You describe SIP/DIP as being 12-16 pins at first while showing 8 and 9 pin packages.
I had work in Texas Instruments semiconductor packaging before. This is a number intensive job. All they care are numbers of chips per day output. All the chips made then store inside the warehouse waiting to ship out to customers in waiting. Sometimes they would purposely ram up production not to ship out but to keep as surplus stock. Once the target numbers achieved, they would declare mass unpaid vacation to all the production workers.
On the other end TI won a LOT of business by being cut throat in its pricing. The FAA contract for the American inter route computer around 1967 say. Sylvania chips were faster.
Thanks, Jon! I had no idea what went into those little squares on the MoBo. Now I have a better idea.
I hope I'm not the only one who thought of anti-static bags and bubble wrap when they first saw the title. 🙄
You aren't the only one I was working 4 the "Blue Co.," For several years and only learned about it shortly before I transferred to East Fishkill
Great video! By the way, in the context of chip design, via should pronounced as vee-yeah, not vah-yeah.
excellent as usual!
Nice video, just one thing...
At 11:10 you're not showing gullwing style pins, but J shape... those are made to be socketed or soldered and were sometimes seen socketed on fancier motherboard as BIOS chips.
Those boards often came with a second spare backup chip.
Basically the predecessor of dual BIOS.
About recent adoption of TSVs, they are an absolute nightmare for the back-end engineers. Being a floorplanner, seing a nice rectangular die being punctured with 20000 no use holes is still the stuff of nightmares, even after taping out 2 chips with TSVs. Random timing fails never on connections before seen in previous chips requiring changes to RTL to increase latency.. power grids having to do a jiggle around holes and sometimes introduces crosstalk to low voltage sectors.. and the tools being absolutely unprepared for these kind of situations.
I was watching DankPods recently, and he opened a knock-off handheld game where they didn't even package the microchip. it's just glued to the board all exposed. And I don't mean they covered it in glue, it's just held on with a drop underneath it. I still can't get over that horror lol.
Integra Technologies is supposed to be building a huge backend plant close to where I live.
Thank you for the detailed explainer
Beautiful video.
Wonder how many college syllabuses refer to this channel. I bet there's a lot of them. Unmatched coverage of the history of the industry and all around good work.
Probably none, EE degrees don't really cover that stuff (I think they should a bit) but also these videos are not quite accurate enough for someone looking to work in the industry to use as a reference.
Nice video, I wish you could shed the time constraints and could have gotten into bonding more. I bet it’s fascinating.
Great video on the history of packaging.
What I don't understand and amaze me is how they can connect 2000+ leads from a chip to the outside world, are they still connecting to the edge of the IC with some bound wires or welding the chip to the packacge and at what kind of pitch density, how many layers are built into a carrier. What can be the cost of the package on a 2000+ pins CPU?
I'm looking forward for your next videos.
As I understood, chip is soldered directly to the package. It's being made itself like a BGA at first, then flipped upside down and have its balls solfered to the inside ends of the pins of the package.
Well done!
In flip-chip, BGA, or PGA, is the die connected through to the packaging via solder balls instead of bond wires then? I'd love to see a picture of the back of these things; the connection side, with the die and the connection to the packaging visible. Is it really possible to just glue a ball of metal to a silicon die like that? Fascinating.
you missed the glob top packaging where the bare die is wire bonded to the PCB itself and then epoxied to the PCB.
Actually he mentioned that but the picture shown was not for that technology. I can't be sure if it was a misunderstanding on his part or maybe a mixup in the production of the video. On the whole he does a good job.
Interposer don't have to be silicon, and is worth mention, because TSMC is using not silicon version a lot in finout design, cheaper, smaller, lighter. And is use in eg AMD Radeon RX 7900 XT/XTX to connect external memory controllers with cache. There are leaks that saying this are made so cache can be stuck on them (as 3d v-cache in Ryzen 5800X3D). And many with organic substrate are used in phones eg Apple using them for many years (chip on chip, when bottom is connect to interposer which is bigger and added connection to top chip around... weird but heat is [I think] main reason what is on top).
17:30 looking forward to your video on 3D integration and die stacking!
Super interesting as always! Question though (maybe I missed a comment): is it not "lead frame" as in the metal and not lead as in "leading"? Although that sounds a bit weird since the leads are connected to it... Although, I'm being told they are called leads as in the metal?? Hold on, what the h...?
yes more packaging please
Hi, I got a question! You mentioned putting the PCB board in an oven thingy as a way to solder everything in one go but, how can you melt the lead with enough heat without destroying the delicate IC?
Yes. As you point out it is a difficult problem. It is handled by controlling the rates of temperature rise/fall. Peak temperature and dwell time at peak temperature. Moisture content must also be controlled.
16:40 - package on package is a pain in the neck to do signal analysis / reverse-engineering inter-package communication . The techniques to interpose are currently risky and expensive to undertake, how I do miss DIP packaging so.
small correction, the chip shown at 11:08 is not a SOP, it is a SOJ - small outline j-lead package. It's main characteristic is that the pins are in the shape of the "J" letter and curve in under the chip. They use less area but they are taller than normal SOP chips. There's also a quad version known as PLCC which I loathe with a passion.
I suspect their main advantage over gull wings is that they can be socketed rather effortlessly, there used to be PC expansion cards that used SOJ sockets for memory expansions, but I've also seen a BIOS chips using PLCC sockets.
6:13 Is that orange thingy the reason why AMD Ryzen branding is orange too?