Powerful Knowledge 6 - Gate drive design
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- čas přidán 16. 01. 2023
- A gate drive circuit in a power electronic system needs to operate reliably on the boundary between low voltage control electronics and the high voltage, high stress power stage. It is subjected to high stress levels and must respond correctly to switching signals with nanosecond timeframes.
This is episode 6 of our powerful knowledge series and we discuss gate drive design in some detail including an example of a custom SiC gate drive design running in a 2kW LLC converter with 600V input.
#netzero #stemeducation #powerelectronics #knowledgeispower - Věda a technologie
Please do another one on the gate driver circuit design step by step with an example.
Hey guys thanks for this series it’s excellent! Would love to see more videos on gate drive design with emphasis on the different protection mechanisms that can be implemented. Again, thank you!
Thanks for your great feedback. What sort of gate drive protection mechanisms are you interested in most?
@@ElectronicmindsUK hey guys sorry for the late reply
To be honest if you could do the following that would mean the world to me
1. Overcurrent Protection (OCP)
2. Short-Circuit Protection (SCP)
3. Under-Voltage Lockout (UVLO)
4. Over-Voltage Protection (OVP)
5. Thermal Protection
6. Desaturation Protection (DESAT)
7. Dead-Time Protection
8. Phase Loss Protection
9. Reverse Voltage Protection
I know that’s allot of material so that being said 123456 are by far the most important. Worked schematic examples of each would also be amazing
Hey guys,
Just wanted to check in to see if this is something that you would still be interested in doing a video on. I understand there were allot of protection systems listed. I think an episode that focuses on the major protection mechanisms used in industry with some accompanying circuit simulation would be awesome. There’s not that much gate drive protection videos online and the few that are are pretty poor in my opinion.
Thanks for the excellent series, it’s really helped me gain knowledge in power electronics
Doron
Great series. I remember signing up for it while at Nottingham and glad to see it on youtube now.
I have a question - what is the path for the common current during the switching event?
The capacitance from switching node to chassis is what is getting charged. What are the sources and the path for that current?
The source of the common mode current is anything which can result in current flowing in earth. In isolated supplies, we tend to look at the common-mode current generated from a fast edge on the primary winding coupling current into the secondary and also the cooling tabs of power transistors coupling noise from fast moving drain nodes onto heatsinks. Both these mechanisms ultimately couple current into earth via parasitic capacitances. It is also why sometimes earthing heatsinks directly can provide a direct path for common-mode current flow.
Thanks for sharing.....
You are welcome Ahsan
Does it help to put Y caps along with the common mode choke at the gate drive isolation barrier input and at the gate power supply input to provide a path for the common mode current to return back and reduce the loop area?
We have experimented with exactly that and I believe it does help. I don't have any data yet to confirm this though.
how to design switching frequency max 400Khz of gate dirve circuit in power electronics system.
The process would be similar to other gate drive designs, you need to set the drive voltage levels (uni-polar or bi-polar), drive strength etc and work out the power requirements of the gate driver - these often scale with frequency. 400kHz PWM is a time period of only 2.5us so you also will want to ensure good drive strength to keep edges as sharp as possible and minimise miller induced effects.
The design of the gate drive will depend on the type of device you are driving too.