This is a very good PCI refresher series! You mentioned that the root port stores the range of MMIO addresses assigned to downstream devices. During BIOS, the enumeration process can make sure that all downstream devices get consecutive MMIO spaces assigned. The range values in the root port can be accurately programmed. What happens if at a later stage, one of the downstream devices is removed and another one, which requires significantly more MMIO space, is hot-plugged in? The MMIO space assigned to this new device might not be adjacent to other sibling device. How does the root port store the (now fragmented) range?
BAR only stores Base address of the MMIO region that has to be mapped, but where is Length Stored?, eg where is 1MB or 4KB buffer information is located. Is there a Length Field to display the Length of MMIO region requested? Got it ...Pre-fetchable Memory Base/Limit.
When you write all 1's to a BAR and read it back, the trailing 0's indicate the size of the BAR. For example, if we write 0xFFFFFFFF to a BAR and read it back, and it shows 0xFFFFF000, the size is 4K (12 trailing bits are 0's and 2^12 is 4K). Then the BIOS programs the base address in the upper bits (upper 20-bits in the case, since the lower 12-bits are always 0s). This would imply that the Base Address of a BAR range is naturally aligned. In other words, if the length is 4K, the base address can start only on a 4K boundary.
Finally I understand the logic of MMIO. THANKS!
Great videos, Most valuable Informations, these are the "MISSING LINKS" of the "BIG PICTURE" . Great work, expecting more videos, THANK YOU SO MUCH.
tons of information with practical values !!!
Thanks a lot for the excellent tutorials.
Thank You for providing this very informative video!
Thanks a lot for the detailed explanation.
Very Useful Videos..
It’s a very informative video. Thanks a lot.
Good explanation.Please share some videos for SAS (serial attached SCSI).
This is a very good PCI refresher series! You mentioned that the root port stores the range of MMIO addresses assigned to downstream devices. During BIOS, the enumeration process can make sure that all downstream devices get consecutive MMIO spaces assigned. The range values in the root port can be accurately programmed. What happens if at a later stage, one of the downstream devices is removed and another one, which requires significantly more MMIO space, is hot-plugged in? The MMIO space assigned to this new device might not be adjacent to other sibling device. How does the root port store the (now fragmented) range?
BAR only stores Base address of the MMIO region that has to be mapped, but where is Length Stored?, eg where is 1MB or 4KB buffer information is located.
Is there a Length Field to display the Length of MMIO region requested? Got it ...Pre-fetchable Memory Base/Limit.
When you write all 1's to a BAR and read it back, the trailing 0's indicate the size of the BAR. For example, if we write 0xFFFFFFFF to a BAR and read it back, and it shows 0xFFFFF000, the size is 4K (12 trailing bits are 0's and 2^12 is 4K). Then the BIOS programs the base address in the upper bits (upper 20-bits in the case, since the lower 12-bits are always 0s). This would imply that the Base Address of a BAR range is naturally aligned. In other words, if the length is 4K, the base address can start only on a 4K boundary.
Is Root port BAR and Prefetchable Base Register have same values?
Could you please also provide some insight into MMIO with SR-IOV and other dependency to have SR-IOV VFs configuration with virtual machine.
I got a doubt why Type 0 config space has 6 BARS and Type 1 has 2 BARS
Hi sir, very nice explanation. But diagrams are not clear and try to use little big font.