When dealing with similar issues, I've found TI app note AN-2162 to be invaluable. It presents some straightforward formulas and worked examples that can be used to directly calculate the values for the filter components with minimal fiddling and fuss.
Basic Filter have often an impedance of 50 ohm. Therefore the Filter calculation ist also different. But it is also possible to do it with the RF wallpaper. Very interesting is the Design of a wideband blocking for a Bias-T. Best regards Thomas
@@thomaseichstetter6777 Thank you for your response. Can you explain why a volt noise induces a current going in every direction from an RF point of view? You mention that about the voltage drop accross the input capacitor, I don't understand what you mean by "a RF point of view"
You google the part number and find the impedance graph on the manufacturers web site. eg CL05A105KP5NNNC. Don't buy from a company that doesn't have the information posted unless you don't care about it.
I have a master set of ipn's this is pre-qualified parts and testing esr and generating proper data set is a part of this. Also in general a ceramic cap of a given package size and value falls into an apx esr range to expect. Kinda like you can make assumptions on response with X7 / X5. Most the ones that fall outside that range are of very poor quality. Also when it comes to preparing for production we have stages EVT1-3, DVT1,DVT2(if required), PVT, production. Most of the time emc/EMI is pre-tested during end of dvt. Final BOM changes are put in place for PVT, this is also when the production line is setup and generally speaking the only difference between pvt and full production is the size of the batch. A normal PVT run is a few hundred units. Production orders are in the range of 3-6mo of projected sales. This can be a tens of thousands of units. This filter layout is useful I actually add a similar filter layout to all my RF IC power inputs with simple jumpers. As a fallback to help decouple rf feedback in the rare case it's a problem usually cellular modules can be a headache in 2nd and 3rd harmonics when using sub 900mhz bands. I find some SMPS and modules can self sync and create crazy harmonics that can become a headache to track down.
Hi sir, I'm using fixed LDO which input is 5v and output is by default 3.35v . If we change in code it boost up to 4.45v . What happens is if I give 5 v input through rps , the output will be 2 v . So, it will not able power supply for other sections. Can you tell me the issue
i didn't understand well the video. I don't know if the guest is too smart and thinks other people know what's going on so he didn't explain or he's not good at explaining things. i also notice robert always ask so what's the solution or what should we do in that case hh If he didn't ask those question the guest will not answer at all hh. but good video anyway. thanks
Wrong!!! Did he include derating of components? I do not see this, so 1st problem and this could have a big impact. 2nd problem, less impact, in the last simulation he used 50 Ohm but in real LISN for common mode is 25 Ohm and for differential is 100 Ohm (seen from input side of the mains if you have doubel LISN construction) but he simulated at 50 Ohm which often is not the case.
To your first point: You are right that components experience derating; capacitors become smaller when you approach their rated voltage, and inductors have lower inductance when you drive current close to their saturation point. However, in this example, we are still far from this point. If you have a project where derating is a concern, you can measure it with a VNA or equivalent equipment and plot it in the RF-Wallpaper. To your second point: The simulation shows the result of a VNA measurement compared to the simulation. A VNA has an impedance of 50 Ohms. When you want to simulate with interference and measurement later, you are correct. But in that case, I would use the complete model with lines and the blocking network, also measured with the VNA. Best regards Thomas
@@thomaseichstetter6777 You answer is generic. That depends there are different characteristics. For capacitors it depends what dielectric is used and for inductors what type of core. You could have your caps 50% of nominate vlaue becouse it have like 40-50% of rated voltage on it. You should always count derating or make a statment that you are not including it and real attenuation could be lower!
@@jaro6985 For people that do not know this it should be mentation that is withouth derating. You need to say what is not counted in the testing/simulations and that is fine but there should be a statement because results could be different if someone want to make similar. As you wrote there is many details but some have more impact then others. Regards, MJ
I think this is partially caused by him getting interrupted so often. When you lose your train of thought, it becomes difficult to stay consistent with explanations.
That last mechanical demonstration setup, is a wonderful way of showing the lumped analogies between electrical and mechanical domain!
Already waiting for the common mode filter video. Excellent visual explanations here.
Excellent video. Great presentation from Thomas and super helpful questions from Robert. I've learned something about EMC. Thank you.
Great stuff! Not easy to make these topics sound simple but you two managed!
Greetings from Türkiye. Thank you for sharing your experiences and knowledge.
Great! I vote for common mode too
I would say there are still many topics you should discuss. The video was outstanding and very clear. Thank you and more please
When dealing with similar issues, I've found TI app note AN-2162 to be invaluable. It presents some straightforward formulas and worked examples that can be used to directly calculate the values for the filter components with minimal fiddling and fuss.
Literally been using the same application note
Nice and interesting presentation! Thx for sharing!
great video, I hope you make me one for common mode soon
Finally you came up with EMC .. great 🎉... please one request can you do some video with SMPS magnetics design
Great Analysis!
Robert, I would try to let your guest follow his track a bit longer before you intervene with questions.
Nevertheless liked the video very much.
Ohh my god I'm looking this video thanks..
Great video! I was curious of the rf wallpaper but couldn’t find it on Thomas web site. Can you please post a link. Thanks!
Thank you for watching. Just click on the Downloads button: emv-wissen.de/wp-content/uploads/2024/06/RF_Wallpaper.pdf
@@RobertFeranec Ah, the download button is not visible on a mobile device, but it is shown on a PC!
What is the difference between an EMC filter and a basic filter ?
Basic Filter have often an impedance of 50 ohm. Therefore the Filter calculation ist also different. But it is also possible to do it with the RF wallpaper. Very interesting is the Design of a wideband blocking for a Bias-T. Best regards Thomas
@@thomaseichstetter6777 Thank you for your response.
Can you explain why a volt noise induces a current going in every direction from an RF point of view? You mention that about the voltage drop accross the input capacitor, I don't understand what you mean by "a RF point of view"
Unfortunately very rarely do manufacturers of ceramic caps talk about ESR on datasheets... how are we supposed to know this witchcraft 😊
You google the part number and find the impedance graph on the manufacturers web site. eg CL05A105KP5NNNC.
Don't buy from a company that doesn't have the information posted unless you don't care about it.
I have a master set of ipn's this is pre-qualified parts and testing esr and generating proper data set is a part of this.
Also in general a ceramic cap of a given package size and value falls into an apx esr range to expect.
Kinda like you can make assumptions on response with X7 / X5. Most the ones that fall outside that range are of very poor quality.
Also when it comes to preparing for production we have stages
EVT1-3, DVT1,DVT2(if required), PVT, production.
Most of the time emc/EMI is pre-tested during end of dvt. Final BOM changes are put in place for PVT, this is also when the production line is setup and generally speaking the only difference between pvt and full production is the size of the batch. A normal PVT run is a few hundred units. Production orders are in the range of 3-6mo of projected sales.
This can be a tens of thousands of units.
This filter layout is useful I actually add a similar filter layout to all my RF IC power inputs with simple jumpers. As a fallback to help decouple rf feedback in the rare case it's a problem usually cellular modules can be a headache in 2nd and 3rd harmonics when using sub 900mhz bands. I find some SMPS and modules can self sync and create crazy harmonics that can become a headache to track down.
Common mode noise is generally pretty easy to deal with
Hi sir, I'm using fixed LDO which input is 5v and output is by default 3.35v . If we change in code it boost up to 4.45v . What happens is if I give 5 v input through rps , the output will be 2 v . So, it will not able power supply for other sections. Can you tell me the issue
i didn't understand well the video. I don't know if the guest is too smart and thinks other people know what's going on so he didn't explain or he's not good at explaining things.
i also notice robert always ask so what's the solution or what should we do in that case hh If he didn't ask those question the guest will not answer at all hh.
but good video anyway. thanks
Clever people usually have this problem... they cannot sympathise easily with us average ones😂
Wrong!!! Did he include derating of components? I do not see this, so 1st problem and this could have a big impact. 2nd problem, less impact, in the last simulation he used 50 Ohm but in real LISN for common mode is 25 Ohm and for differential is 100 Ohm (seen from input side of the mains if you have doubel LISN construction) but he simulated at 50 Ohm which often is not the case.
To your first point: You are right that components experience derating; capacitors become smaller when you approach their rated voltage, and inductors have lower inductance when you drive current close to their saturation point. However, in this example, we are still far from this point. If you have a project where derating is a concern, you can measure it with a VNA or equivalent equipment and plot it in the RF-Wallpaper.
To your second point: The simulation shows the result of a VNA measurement compared to the simulation. A VNA has an impedance of 50 Ohms. When you want to simulate with interference and measurement later, you are correct. But in that case, I would use the complete model with lines and the blocking network, also measured with the VNA.
Best regards Thomas
@@thomaseichstetter6777 You answer is generic. That depends there are different characteristics. For capacitors it depends what dielectric is used and for inductors what type of core. You could have your caps 50% of nominate vlaue becouse it have like 40-50% of rated voltage on it. You should always count derating or make a statment that you are not including it and real attenuation could be lower!
There are a million details that could be discussed, leaving out de-rating here is perfectly acceptable.
@@jaro6985 For people that do not know this it should be mentation that is withouth derating. You need to say what is not counted in the testing/simulations and that is fine but there should be a statement because results could be different if someone want to make similar. As you wrote there is many details but some have more impact then others. Regards, MJ
I am sorry to say. He could have good experience in EMC but the explanation would be better
I think this is partially caused by him getting interrupted so often. When you lose your train of thought, it becomes difficult to stay consistent with explanations.