This is a great lecture. Thanks for sharing these outside of Cornell. I am working on an FPGA video processing project right now, and these lectures greatly enhance my understanding of the architecture and Verilog code.
Lichtenberg figures in reverse. A charged binary array, seeded and allowed to discharge in the frame buffer. Sorry for the random comment, it just occurred to me while watching the lecture. Starting my second time through these lectures as edutainment for an aging analog engineer seeking digital wisdom. ;) Thank you for posting these Professor Land.
Hi, Thank you for sharing this with us. I'm following your lectures on this course and started lab1, actually i just finished it but still have some problems. The following link is a video that shows results for the 1-D CA for rule 153, implemented in Spartan 3E kit from Xilinx. The results that came from simulation are correct (when displayed on MATLAB) but the actual result on the VGA is different. I wonder what's the best way to debug this? should i read the contents of RAMs and send them to PC using UART to compare against expected pattern? or use something similar to signalTab from Altera? BTW, what's the alternate in xilinx ? is it chipscope? Link: czcams.com/video/_NgbUKL5Yts/video.html
I know very little about Xilinx tools. But it sounds like the mapping from RAM to VGA may be off. YOu could simullate the VGA driver as well and check for bad addresses or data mapping.
the vertical lines and the triangles that contain them should all be white (binary value of 1'b1). Also most of the triangles in the first "row" of the screen shoudn't have been there, all should be white. To better understand what i mean, can you please check the following picture? it contains the expected output from a MATLAB model. BTW, the output from simulation exactly matches this MATLAB model. drive.google.com/file/d/0B06JMmlmS4OlMjFNVFl6WXZUd1k/view?usp=sharing
This is a great lecture. Thanks for sharing these outside of Cornell. I am working on an FPGA video processing project right now, and these lectures greatly enhance my understanding of the architecture and Verilog code.
Lichtenberg figures in reverse. A charged binary array, seeded and allowed to discharge in the frame buffer. Sorry for the random comment, it just occurred to me while watching the lecture. Starting my second time through these lectures as edutainment for an aging analog engineer seeking digital wisdom. ;) Thank you for posting these Professor Land.
Love his energy! really!!!
Bruce is a hero!
Thanks, but I have to tell you that knowing I am being recorded makes me a better lecturer.
This guy is a genius. The reason why I completed my Main project ...great tutorials. :D
I get lost in your shirts
Why is he using an unlock bit? Why not just control the clock to the CPU?
want to give a time stamp?
+Bruce Land @19:15
+Marc Jacobi A better way to do it is to use dual port memory
+Bruce Land gateting a clock is a bad idea
+Bruce Land ok, why? I know a couple of designs that do that (ZX Spectrum ;-)
Thanks for info on str_catination in Verilog via assign ..
Hi,
Thank you for sharing this with us. I'm following your lectures on this course and started lab1, actually i just finished it but still have some problems.
The following link is a video that shows results for the 1-D CA for rule 153, implemented in Spartan 3E kit from Xilinx.
The results that came from simulation are correct (when displayed on MATLAB) but the actual result on the VGA is different. I wonder what's the best way to debug this? should i read the contents of RAMs and send them to PC using UART to compare against expected pattern? or use something similar to signalTab from Altera? BTW, what's the alternate in xilinx ? is it chipscope?
Link:
czcams.com/video/_NgbUKL5Yts/video.html
I know very little about Xilinx tools. But it sounds like the mapping from RAM to VGA may be off. YOu could simullate the VGA driver as well and check for bad addresses or data mapping.
Looks OK to me. what is wrong? The vertical lines?
the vertical lines and the triangles that contain them should all be white (binary value of 1'b1). Also most of the triangles in the first "row" of the screen shoudn't have been there, all should be white.
To better understand what i mean, can you please check the following picture? it contains the expected output from a MATLAB model. BTW, the output from simulation exactly matches this MATLAB model.
drive.google.com/file/d/0B06JMmlmS4OlMjFNVFl6WXZUd1k/view?usp=sharing