CppCon 2015: Michael Wong “C++11/14/17 atomics and memory model..."
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- čas přidán 19. 10. 2015
- www.Cppcon.org
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"C++11/14/17 atomics and memory model: Before the story consumes you"
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Presentation Slides, PDFs, Source Code and other presenter materials are available at: github.com/cppcon/cppcon2015
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In 2011, C++11 atomics offered three memory models but 6 settings. Most compilers have started implementing most of these (relaxed, seq_cst, acquire, release, acq_rel) but not consume (For that you will need to see Paul's talk which naturally follows this talk.) For this, I will deep dive into what each memory model setting means (especially for Games Development and low latency, a new SG14 in the C++ Standard) and how C++11 atomics are used to improve handling of mutable shared state. We have improved on it in C++14 and have more crazy things planned for C++17. I will also look at how C++ atomics are a natural precursor to SG5's Transactional Memory which was approved in Lenexa for publication.
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Michael Wong is the CEO of OpenMP. He is the IBM and Canadian representative to the C++ Standard and OpenMP Committee. He is also a Director of ISOCPP.org and a VP, Vice-Chair of Programming Languages for Canada’s Standard Council. He has so many titles, it’s a wonder he can get anything done.
He chairs the WG21 SG5 Transactional Memory and SG14 Games Development/Low Latency, and is the co-author of a number C++11/OpenMP/Transactional Memory features including generalized attributes, user-defined literals, inheriting constructors, weakly ordered memory models, and explicit conversion operators. Having been the past C++ team lead to IBM’s XL C++ compiler means he has been messing around with designing C++ compilers for twenty years. His current research interest, i.e. what he would like to do if he had time is in the area of parallel programming, transactional memory, C++ benchmark performance, object model, generic programming and template metaprogramming. He holds a B.Sc from University of Toronto, and a Masters in Mathematics from University of Waterloo.
He has been asked to speak at ACCU, C++Now, Meeting C++, ADC++, CASCON, Bloomberg, CERN, and many Universities, research centers and companies.
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Videos Filmed & Edited by Bash Films: www.BashFilms.com
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Before watching this video, you'd better have read the book c++ concurrency in action or the memory model in Cplusplus reference.
This talk introduces the memory model of C++11/14/17 on a high level. The speaker
introduces a lot of concepts and definitions of the design of the memory model of
C++11/14/17, like: data race introduces sequential consistency, what is memory model.
it's worth watching though the content arrangement seems a little messy.
Really really hard to follow with the jumping between slides and spending less than 2 seconds on some slides.
It would have been better to drastically narrow the presentation's reach and take time to explain what was exposed.
I thought that Michael did a pretty good job with this presentation. If people feel that he's going too fast with the slides, we have the option to pause the video and go over them carefully which is well worth doing.
actually really good talk
What about the specific link for the slides instead of the generic url? Thanks.
36:37 👍 good use of "tomfoolery"
I think 2 of 4! interleavings is a bit misleading, as there are 4! permutations of those 4 statements in each compilation unit, the number of possible interleavings is much higher than 4!... (he says this statement). I think we should clarify it.
Actually 70 = 8!/4!4! possible interleavings. For n and m statements that should be (n+m)! / n!m! because N(n+1, m+1) = N(n, m+1) + N(n+1, m) (start with either thread).
Hmm. I just don't understand why is sequential ordering slower, when the only difference is that compiler is not allowed to reorder writes (well ... or independent reads). I guess it depends in cases where an atomic variable is used as a spin-lock and all threads need to lock two of them always in order. I'd like to have some real-world examples cause I never used atomic variable as a synchronization mechanism, only as something that can be read and written by multiple threads (e.g. terminate flag, proceed flag in condition variable, etc.). :-( Which is something I expected from this talk. Cause just ordering of instruction likely doesn't have any significant performance impact.
"how dare you!" hahaha
I don't think the wording "happens-before" makes much sense, given the example in 50:11, if #4 actually physically happens after #1, then there's no way they're going to synchronize with eachother. The load acquire can only get the data of the store release if the store happened early enough compared to the load. The precise timing will depend on scheduling and how much work the threads have to do to get to that point.
czcams.com/video/A8eCGOqgvH4/video.html
I'd recommend newbies go watch the linked video first before this one.