How to Properly Terminate a Clock Signal by Identifying Common Signal Integrity Issues

This video describes how to analyze and properly terminate a clocking waveform. A good clock waveform is properly terminated when the output impedance of the driver and series resistance exactly matches the impedance of the transmission line. When the series resistance is too low for the transmission line, the waveform will exhibit overshoot, undershoot, and ringing. When the series resistance is too high, the waveform will exhibit a step on the rising and falling edges. By identifying the waveform characteristics, and then adjusting the series resistor up or down accordingly, you can often alleviate the most common termination-related issues in your circuit.
Presented by Ron Wade, clock expert at IDT.
For more information about IDT’s leading portfolio of clock buffer products, visit www.idt.com/pro....

[@t1d100]

I am building a Schmitt Trigger to clean up the signal on a DIY GPS Timing Reference. I thought that my poor waveform issues were likely related to incorrect termination. So, I watched your short video. It was two minutes of exactly what I needed!
I tested the S-T with my function generator. By varying its output resistance (50/600 Ohm button) and adding a variable resistor in series and parallel after the Schmitt Trigger, I was able to effect/improve the waveform's shape. Thank you!

[@timpeng1269]

Great. Drop us more like this.

[@SOP83]

I want to know how the capacitor rating at the load point affects skew/slew in relation to frequency.
Some designs call for 0.1uf others 0.001uf. Some don't even use a capacitor.

[@vincentchung6316]

The result assume unterminated transmission lines. If probe input impedance is terminated at 50 ohm, then these plots are incorrect...

[@abhijithprabha6377]

thanks

[@CodeJeffo]

Nice.

[@zhitailiu3876]

What if it's a data line? Do we need to put series resistors on both sides of transmission line?

[@paulf1071]

Not sure, but for matching I'm guessing there are many similarities between a CLK pulse-train and a data line. One other important aspect of a high frequency data line would be the slew rate (outside of maximum specs, and the Rx may interpret an incorrect logic level).

[@conesillyvalley7182]

For bidirectional data line, keep lines as short as possible, match the data lines length within 5mil and then put the Rs in the center of data lines