Capacitors are terrible at remembering data. But for this reason we continue doing it.
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- čas přidán 11. 09. 2024
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In this episode we discuss about Dynamic RAM, and lear about all the fundamental-level challenges that makes it slow compared to Static RAM.
It seems your true interest is in electrical/computer engineering, vs. CS - this is a VERY welcome addition to CZcams, where this kind of clear, concise, well-animated, and perfectly-paced content may already exist for CS, but is essentially nonexistent for CE. Please don't stop :)
I’d love to learn more about this ultra low level stuff in computers
I just take it for granted but someone had to think about it
Ben eater?
You might also like Ben Eater
Words cannot describe how much i love your videos, please never stop.
That's what a wordline is for, i suppose 😇😁
@@Mrfebani I'll try opcodes next time lol
Never stop me loving you
I am an electrical engineer, have some knowledge of some programming and hardware description languages, have been working for many many years, and am familiar with many educational materials and lectures. I can tell you this much, your way of presenting and showing things are by far the most intuitive and understandable I have ever seen. I am also familiar with the Branch Education videos, which provide an incredible level of detail and make it tangible to the viewer. But your presentation goes so much deeper into the basics that not only newcomers but even experienced people can't help but say FINALLY. I take my hat off to you and your work. The greatest respect!
PS: Maybe you could make a video about why NAND flash or memory in SSDs, for example, is slower than DRAM/SRAM. Especially in view of the fact that you have described very well how SRAM gets its "storing" property when reading, a further presentation could show that it is not comparable to NAND flash or non-volatile memory. In my opinion, this would be a good bridge to explain the last bottleneck (memory) in terms of CPU(cache)->RAM>non-volatile memory.
I don't have any actual degrees, but I do have the knowledge and understanding of most of these fields from computer science to software and hardware engineering and I was thinking the same thing in regard to volatile vs no-volatile memory. I'd also be curious in a fine detail explanation of atomic operations.
When I was writing a piece about Commodore (my background is in economics), I always thought it was weird for Jack Tramiel, the cheapest man in the world, to use SRAM in his first 2 successful home computers. Seeing how complicated it is, and the necessity of DRAM refresh, I understand why now
Proud owner of a Commodore VIC-20 and Commodore 64, here 🙋🏽♂️
Wow, I had no idea that my RAM was so sketchy! Now I am frightened! 😆
Yeah, I was surprised as well! That would explain why servers use way lower clock speeds and ECC
@@el_quba Hmmmmmm... I didn't know that about servers!
@@oglothenerd For example, majority of DDR5 server sticks stay below 5000MT/s* while consumer DDR5 quite often has 6000MT/s* and some even go above 7000MT/s*.
This of course comes with instability issues (even without current Intel blunders) so PC build guides recommend keeping clock speeds modest for professional users. And now I know where that instability comes from!
* I use MT/s here, which is likely the correct unit, but RAM clock speed units provided in specs are a hot mess, so take the unit with a grain of salt. The main point still stands tho.
@@el_quba This is good info to know! Thank you!
Manufacturers lately have not trusted their capacitors lately. Based off The refresh cycles every 30 ms And they're adding error correction to the die in ddr5.
There’s a type of memory in-between dynamic and static RAM called “lambda memory”.
It uses a reverse biased diode as a constant current source and a pair of depletion mode mosfets.
It’s called a lambda memory cause the current through it rises then falls with voltage. Because of parasitic resistance/leakage the current actually rises then falls then rises again. Due to this it can store 3 voltage states at constant current (LOW, MID, HIGH).
It also has another enhancement mode mosfet for reading/writing.
In total, 1 diode, 2 depletion mosfets and 1 enhancement mosfet gives 1 memory cell that has 3 states and uses 7 semiconducting junctions. Compared to a normal static memory cell that has 2 states and uses at least 12 junctions, it stores 1/3 more data in 1/2 as much space. Quite a bargain. Unfortunately, it is not in use due to very tight tolerances for manufacturing each memory cell since the nonlinear behaviour of the silicon is sensitive to even slight imperfections or doping variations.
You basically teach people from grounds up. And you don't hide it behind paywall. Thank You.
Happy to help!
Your videos are always very clear, and I understand them so well.
Thank you for doing this for us!
Very, very well done!
I'm also a software engineer - albeit one hiding a logic analyzer and soldering iron behind his back. So a few comments and nitpicking.
At the level of your video I think the finer details of newer memory types such as DDR memory imho can safely be ignored. That's basically additional details that should be left for a closer look.
Memory refresh is complicated and some memory controllers have ample options to configure refresh. For many if not most hardware this is undocumented black magic. This kind of setup is usually performed by firmware in early initialization right after the CPU itself is ready. Depending on the CPU the cache SRAMs might contain junk such as data with invalid parity or ECC which needs to be cleared first because the CPU can perform a cached memory access without blowing itself up. Even an implicit memory access such as for the stack could do so, so at this stage subroutine calls are taboo. You'd think hardware'd make that easy but wiring a reset line to everything that needs to be initialized for use once after reset is something that gets harrdware guys rioting and point their fingers at the software guys "you do it" 🙂
Next memory controllers. The cache may be working but DRAM still can't be accessed. In older systems that was as simple as writing a few constants into the memory controller. Some systems had to perform strange voodoo to figure out how much memory is actually physically present. Yet more modern systems have feature known as SPD allowing the system to detect the quantity, type and speed of memory. Software then programs the memory controller accordingly. Still no stack access so such code often is a unholy mess of deeply nested C macros. Optimal programming includes the use of features such as interleaving where possible and many more, so it's not trivial Once this has been completed memory may need to be cleared to avoid parity or ECC errors. And after that sanity arrives, everything else is much simpler now that "normal" programming is possible.
Some very old systems are nice in that they don't need any software initialization at all for their memory controller. The hardware is (in hindsight) unsophisticated enough to just know what to do without being told to.
Finally caches may not always consist of SRAM. One of the systems I worked with had three levels of cache. The CPU was switched to a different architecture and the new CPU architecture had a different bus, so conversion logic was needed. But that logic slowed down memory access. That was fixed / kludged (you choose the term) by adding a 64MB L4 DRAM cache. The only DRAM cache I know off but I haven't researched that exhaustively.
Another video that I will watch again and again over time. The recommended two videos are also explanatory.
Yet another absolutely amazing video! I am so happy you make those videos, because they answer a lot of questions that always bothered me but would take hours or days to research. And that visual aspect helps so much!.
Do you plan on making a video about clocks and their role in components? They are seemingly crucial for computers, but don't really appear in your videos to reduce complexity. Yet I'm still curious how clocks keep everything in running and in sync, so such video would be amazing!
Video about Clocks is definitely on my list!
Well suggested! @el_quba
Nice job. You succeed to simplify while remaining complete. Continue in this direction... I would like to see more programmers having interest in hardware mechanics. It really helps understanding complexity and program improvements.
I've been in engineering for over 20 years... and I finally realized where the D and S in DRAM and SRAM come from 😅😂
In Polish, "SRAM" is also a word that means: Im making a sh*t.
@@norbert.kiszka 😂
I always thought it was for Downloadable RAM
You definitely have the best visuals when showing how all of this stuff works
16:53 - in earlier computers, the ram chips handled a single bit of a memory location and you put multiple together to make up the width of a memory location.
The address lines on the chips would only handle half of the address lines and would have pins that indicated whether the value on the represented at that moment a row or a column (RAS & CAS).
I see how scalability of DRAM is so good! You can basically keep the part with mux-demux and sense amplifiers and extend in the other direction, for which only a bigger decoder is needed.
I wonder, on the physical RAM memory chips, does this concept get used? The memory chips themselves are rectangular, so it is tempting to assume that the mux-demux and sense amplifier part is along the shorter side.
I love how clear concepts are presented in your content. Please make a series of OS/RTOS topics.
Hey, you got yourself a sponsorship, well deserved!
This is a very well made video. As an electrical engineering student, I'm sending this channel to all of my classmates for our list of educational CZcams channels
The animations on this video are so smooth and well executed, even tho I already knew most of this it was still so engaging and satisfying to watch
i love your YT-videos. I have always looked for an explanation how the actual hardware of CPUs works. And I always got these zoomed out views that never explain how storage and code actually is stored in hardware. Thanks
This is now my favorite channel.
I don't know... but i subscribed to your channel a long time ago & finished all the Previous videos... still i didn't get it recommended... this Channel is Seriously Criminally Underrated by CZcams algos... your contents are truly unique...
Yeah, I've noticed the algo is not recommending me lately.
I felt bad b/c I thought I hadn't subscribed.
Realized I had subscribed many videos ago.
Good decisions were made.
I really hope you keep making these videos. You have a clear talent for it.
And I LOVE learning stuff like this. I'd much rather watch this than the brain rot BS others are making.
10/10 channel content
Wow, such clear animations to illustrate your treatise! Great work!!
We need this type of explanation 🎉
Very nice description of an issue, I knew only from the design level of CPU's. The Z80 for example, has an inbuilt dynamic RAM logic and refresh generator.
So that is the difference between Dynamic RAM and Static RAM. Amazing!
Please make a video discribing all the type of memories like.. Registers, Cache, Flash, Magnetic disks, Ram, Rom, and comparision in terms of cost speed etc. It will be very helpful...
These types of videos take you deeper into programming. Thank you very much ❤
Since you're usually reading a lot of data at once tho when you do perform a read operation, computers do often cache the data in fairly large chunks, up to a few kb. It makes sense to do that since you're already reading the whole row, each extra byte you grab has pretty minimal cost.
As far as refresh rates go, iirc 50-60ms is a pretty common interval, but you could go lower to like 20-30ms if you were really concerned about rowhammer attacks or similar
Your content is incredible. I did startt getting confused around 8 minute mark. Idk why but all of a sudden it stopped clicking in my head. Just wanted to provide feedback.
Thanks for the feedback, I'd use it to improve in later videos.
i think no-one can make better explaining videos than you. im a fan
i really love your videos. one of my favorite CZcams content right now and i always wait for new episodes. (im from germany btw)
Thanks for the support!
Kindly publish a video on GPU intern workings compared CPU
GPUs need an entire book maybe even a couple of books to explain. Primarily because GPUs rely heavily on fixed function hardware so you need to explain every function how they work and why they are needed.
Simplifying to the essentials to make it understandable to people not involved in designing chips, which is the vast majority of viewers. Great job deciding on what is important to show in detail, and what to show with vague blocks with no internal detail.
This is great. Your explanation was very easy to understand. I wish you had explained the refresher more in depth; it seems quite difficult to make it work with the existing circuitry you explained before.
good sponsor recommendation, thank you
what do you use to visualize these circuitry and animate them?
Wonderful explanation 👏
Cool video. I'm also a software engineer, but I love this stuff.
Keep uploading brother❤
Hmmm for data-storage devices like SD cards or thumb drives, which type of RAM is most often used?
Man, there is no doubt that you do great videos. But I'm really waiting for the "how loops and conditionals work" video. You have promised 😉
Hopefully, that's the next episode. The reason I haven't finished it is because I'm also developing an interactive tool (related to that topic) so you guys can use it in the browser.
@@CoreDumppeddefinitely, that will be a video I'm searching for many years. Thanks, man!
@@CoreDumpped That sounds very tempting!
Fun fact: A MOSFET in integrated circuits is a 4 Terminal device. The BULK. it is just always connected to the gate when it is produced as a discrete device. In the more elaborate icon for a MOSFET, this is made visible.
You can get four-terminal FETs in discrete form. Usually the B terminal is used for biasing. You don't see them often, but they are most common in high-frequency usage where the input signal is so difficult to work with that just putting the correct bias on it is difficult - it's sometimes easier to have the bias voltage entirely separate from the signal path.
Sir I have commented a question on your "How Transistors Remembers Data" video. It would be really helpful if you reply with an answer for that 😊🙏
For the "leaking charge" of the capacitor while not being accessed, is it connected to quantum tunneling?
Please keep making videos like these!
could you make a playlist on your channel with all the videos on your channel, it makes it easier for us to watch multiple videos in a row :D
Great channel, I am just wondering which software you use to make these videos ?
Excellent exposition. Thank you.
Amazing Content of Engineering Education
i love his videos
and appyl logic in minecraft
Can you make a video on unregistered synchronous DRAM, very commonly used in today's consumer devices?
Thanks
your programme is one of the most benificients
Have fallen in love with your videos 😌 ....
"i'm a software engineer, not electrical engineer, so.."
...so i make best videos on youtube on electrical engineering
As a professional JS hater I really appreciate your hardware-related videos, can you recommend any books or other materials for learning more about electrical engineering?
All the time while watching this I more and more get the impression that this is not to dissimilar in concept from how core memory works.
What happens when there is a cache miss during an instruction such as a load or add or sub instructions that has to now use slower ram? Also similarly what happens when it has to use drive - Is that when a process goes D state temporarily?
well the core has an out of order execution unit so it will execute other instruction instead or even switch the thread. there is always time wasted waiting and the trick is to make it do as many as possible.
I would have loved to have these videos for my Masters in Electrical Engineering courses that explain these kind of systems. Thanks anyways!
Thanks for your video,
This is insanely good and in depth
2:32 the transistor model doesn't actually map the gate model of the static ram cells: the transistor model is a double-(cmos)-inverter cell with two access transistors while the gate model is a double-nand cell with no further access method except of course the second input from both nand gates.
Bro is a legend
Yeeaaah i was waiting for this 🎉🎉🎉🎉
🔥🔥🔥🔥🔥
thank you, this is invaluable
Best chanel in CZcams ❤
I am great fan of your videos.. I would have clicked that like button at least a thousand times!!! if possible!
Watching eveery single vid u make so far
U r really amazing
You should put all your videos in a playlist that we can just click and watch sequentially I get I bet you'd get a ton of views.
Another great video on computer science, many thanks1
but isnt a mosfet itself basically a transistor that also acts as a capacitor? because if you for example apply a voltage to the gate and then remove the voltage source, it will still allow current to flow from source to drain due to its capacitance. or am i missing something?
but one thing i dont completely understand is why do we need to precharge the bitlines ? why cant we just read if there is any voltage or not ?
Because as soon as the gate of the MOSFET is opened, the capacitor starts to discharge. The voltage provided by the capacitor is proportional to its charge; so it decreases while it loses charges. In that scenario bitlines would be outputting a variable voltage.
Also, using the bitlines as capacitors doesn't require the process to completely charge or discharge the capacitors, so when those capacitors need to be refreshed at the end of the operation, the process won't require to wait for a fully charge or discharge, which for obvious reasons would take more time than only charging or discharging it "a little bit".
@@CoreDumpped thanks for the reply I think I understand now
I think we need to remove the ghost from the previous write and also bias the pre amps on the edge. The capacitors are charged if not too old. We just want to know the polarity.
One thing to note is that the bitlines, like every other component, have some capacitence. In fact, when you consider that to reach however many gigabits of capacity a modern RAM chip has, a bit line must cross hundreds of thousands of rows, we can see that these are rather large structures, and so the capacitence can be presumed to be quite significant. Did I mention that we also want to make the data storing capacitors as small as possible so we can fit more of them?
What this means is that DRAM capacitors are very likely not large enough to fully charge or discharge an entire bitline, not even close. But they don't need to. If we precharge the bitline to right about the threshold voltage for the sense amplifier to switch one way or the other, then just a small change in voltage is enough to tip the balance and read the bit.
How do you make those animations?
powerpoint
Yeah, everything you watch on my videos are just PowerPoint slides.
love your videos!!
Binge watching your videos 🙂
That's probably why computational RAM exists. Sure, the computations are simplistic compared to a CPU, but a machine built with C-RAM is a whole lot faster than a general purpose computer! 😮
was C-RAM ever implemented in any real microchip I can buy ? I don't think that ever went out of the research phase. I was looking for something and only found the I-RAM concept.
Which ironically was more similar to how a modern GPU works, with a couple of small changes, you can make RAM synchronize with the parallel computation, so you don't need to specifically put the computing Logic near the RAM.
The problem is one of the process node, I bet capacitors suffer from leaks and that require special masking layers on the actual silicon , which would be unnecessary for normal logic, and make the transistors waste more power, as they also leak, but the leak doesn't matter much after the signal passed to the next clock cycle.
There's a reason why the entire industry is going for chiplets, so they can use different kinds of process node in the same design that produces a device.
If you study the story of semi-conductors you always find this split between memory manufacturers and logic manufacturers.
And even if you put logic near the RAM, DRAM is still slow, what we're doing now is putting the SRAM on top of the CPU, thus saving time on signaling. That makes the CPU go way faster, and you can have so much cache that we're literally going from DRAM to SRAM as actual memory, in modern CPUs, the RAM memory is the cache, the external DDR is actually more like disk, or network.
SRAM got so cheap, we just don't use more of it because we ran out of space in the actual die, its 90% SRAM already ! so that's why we're never going to see C-RAM, we have something even better, SRAM. And with 3D stacking like V-Cache , for example, the AMD 7000X3D , we can have the best of both worlds.
And mobile SOCs (system on chips) were already using stacked SRAM on top of the die, like a chiplet, but with an interposer, not literally gluing silicon dies.
SRAM is used more like storage nowadays, everything happens on Static RAM, cache basically solved that problem.
Its all about the data-flow, RAM is slow, but with some "simple" synchronization circuit, you can turn normal DDR into GDDR, which reads the entire memory sequentially, row by row, thus you basically pipeline it, and then you put that in a huge BUS, and then you can have lots of parallel small CPUs working on the entire memory row.
That's what the industry did to GPUs.
Read -> Execute -> Write pipelined. After the first delay, the memory and the "CU" (compute unit) will run synchronized with RAM access, thus effectively working like a C-RAM with 0 latency, but without actually having to put the logic near the RAM, thus using the already developed tech.
Its its faster than a general purpose CPU, because it is not general purpose, it can't do jumps, or branching, it can only execute sequentially, the RAM is not used as "random access", but there are still threads, so it is still random when switching from threads.
We didn't get C-RAM, but we got SGRAM, Synchronous Graphics Dynamic RAM. Which basically described what would be the design of modern GPUs since 2012.
Ironically the most consuming GPUs we have now are going for HBM with is basically SSRAM , synchronized static ram, since 2019, we need so much performance that we're going to just pay the price and actually use Static RAM everywhere, DRAM is too slow, DRAM is "disk".
@@monad_tcpshameless plug: the 32 bit gaming consoles all had half their die dedicated to SRAM ( Jaguar, 32x, PSX, N64 ). PS2 then had chiplets and 1024 bond wires. Nintendo virtua boy had a silicon chiplet bonded to a gallium arsenide chiplet for red LEDs.
I wish I could see a video of how it works GPU and how it communicates with the CPU..
This is so cool!
THANK YOU FOR NOT PUTTING AN X OR K IN ESCAPE😊😊😊😊
Amazing, almost indistinguishable from magic.
Superb brother!! Superb!!
i knew dynamic RAM was sketchy, but i was not suspecting it _this_ sketchy.
I hope they also have error correction.
basic DRAM doesn't, however servers that need to be as stable as possible use ECC DRAM, which sacrifices a small part of the capacity for error correction
8:55 here i don't understood how exactly it re sets i mean how it make the capacitor to its initial state , just like u have simulated at beginning of charging and discharging if u can please explain this also like that
These animations are cool, how do you make them.
masterpiece, keep it up
Yea another dram video, before I try to make Dram on a breadboard.
Yet another banger
After Chrome wrote the video buffer to my RAM, they became self-conscious and detonated me and my computer
Good video, would highly recommend
Capacitors are awesome at storing data. DRAM designs just push them to the edge. If you want to pay more for DRAM, you can get some on a better process and with much lower density but very long storage times. It is just not economical nor necessary. Do refresh times affect you personally or your PC experience? Absolutely not. So while I do agree that DRAMs don’t have very long data retention - they absolutely don’t have to. I am using electrolytic capacitors in a relay computer memory. They retain the state for many hours without refresh. You can stop the clock, turn the thing off, later in the day turn it back on and all the memory and register content is retained.
Awesome video, yet again!
i like how observing the ram basically collapse it like its in super position
Why would you need a Mux-Demux if you can just output or input from the bus? You would want to change one word at a time instead of one bit.
I always wondered how DRAM refresh worked...
That jlpcb gonna save that thx! 👀👍 nice vid 👍
Capasitors dont store the data, they just keep the data line high when readed..
Very helpful! Thank you 😎🤖
thanka sir