Part01 Introduction (HLS Programming with FPGAs)

High-level synthesis, HLS, FPGA, AWS, Vitis, Xilinx
Lecture notes uploaded to my website: sites.google.com/view/ykchoi/...

[@johnnyBrwn]

You're a genius man. You're helping me out a lot in my PhD!

[@satamo1996]

I have Embedded system Engineering course in masters MSC.Thanks for the video.Sincerely.

[@kailuo292]

Thanks for your upload

[@gordonwong892]

Thank you for the upload

[@abuali5513]

Thank you for the clear and perfect explanation

[@psp_online]

Is it possible to design multi-rate systems using Model Composer 'HLS' blocks in MATLAB Simulink environment?

[@Bwajster]

Does Vitis HLS v2022.1 support built-in HLS Functions such as hls::Threshold, hls::Erode, hls::Dilate, hls::Mul, hls::Duplicate, hls::MinMaxLoc, hls::CvtColor etc. ?

[@youngkyuchoi4260]

I am not too sure, but Vitis Vision Library seems to be supported on Vitis 22.2.

[@mehtubbhai9709]

Does all of the 1000s of lines of Verilog code @5.30 in the video need to be generated by hand or is a lot of it boilerplate code that can be automatically generated?
Thanks for the great video 👍

[@saadqayyum2148]

Could you share lecture slides?

[@youngkyuchoi4260]

Sorry for the late reply - uploaded to my website at sites.google.com/view/ykchoi/teaching

[@saadqayyum2148]

@@youngkyuchoi4260 Thanks

[@willcowan7678]

How come verilog is censored in the video? Proprietary?

[@youngkyuchoi4260]

No, I was just making a point that a Verilog design is less readable than an HLS design :)