AMD vs Intel - Intel Are Not Dead Yet (Part 2)
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- čas přidán 16. 03. 2023
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czcams.com/users/timedtext_cs_p... - Věda a technologie
So nice to see someone not only open admit they made a mistake, but then go into a 30 minute video proving why they were wrong and what their new knowledge leads them to think now. This quality is so rare in journalism now a days (especially on CZcams).
It’s like the exact opposite of MLID 😂
God I missed your videos and in-depth commentaries. I sure hope they get released more often as the competition heats up again between the giants.
@CompilationHUB No idea what lies you mean.
@@AM-gf7zv Given that he didn’t reply back, I think we have our answer XD
One thing to note about 3nm is that N3 only has a 5% decrease in SRAM size, and N3E (the higher performance version with better yields and efficiency) has a 0% decrease in SRAM size. The only benefit that AMD gets from going from N5 derivatives to N3 will be power when using SRAM. Costs go up from higher wafer prices and lower yields. N3 for logic, N4 for V-Cache and N6 for IO seems to be the most logical distribution of nodes for the chiplets.
Depending on how good N3E ends up being, it may make more sense for Zen 5 to be on N4P. Excellent performance, yields, and efficiency without exorbitant wafer costs. They should be more than competitive with Intel when using N4P against Meteor Lake. A Zen 6 lineup on N3E or whatever it’s successor might be would be good for going against Arrow Lake and Panther Lake.
Great point, it's why Zen4 V-cache is on cache optimised 7nm.
I cannot see where the TSV for V-cache could be laid out in L3$ less CCX designs.
The common use cases for dense cores, also don't benefit from large caches. If you are constrained by processing that scales rather than memory or i/o, by implication you're working with blocks of independent data which can be sized to fit in caches.
For cloud providers having more CPUs in a socket gives the headroom to run at higher utilisation, while gaining in power efficiency.
I love videos like these, the deep dives. Don't be too hard on yourself, you always come through with corrections. All the love in the world to you Jim, you are the best.
Went from 4 core CCX to 8 cores CCX, then introduced chiplets (CCD + IO die) then 3d-vcache, then Zen-c cores (servers).
Basically introducing something new every Zen release and I'm thinking of what the next thing for Zen5 can be? What is it that is so cool that Mike Clark want to see come to fruition?
AMD has acquired Xilinx so maybe a Heterogeneous design with FPGA as a chiplet (update-able FPGA die)? L4 Cache on the I/O die? RAM Memory die like DDR5, SRAM or HBM (think GB size "RAM-let")? CXL support (Jim showed a chart at 6:00 where they had a CXL enabled benchmark)?
I personally think that Memory is what needs to get redesigned, there are SO MUCH performance latency penalty and wasted energy due to shuffling of data, so much that the CPUs are actually idle for long times!!! Even though they are "100%" utilized they are actually often being "utilized" by waiting and shuffling data NOT computing it when being at 100%.
So the "low" but not so low hanging fruit is a Memory architecture redesign.
I believe that we will see Zen5 with RAM die of some sort (HBM?), smaller total L2+L3 cache (smaller L3, no L3, same/smaller/bigger L2 whatever makes sense) that Jim mentioned.
And here is a possible consequence and the kicker of having RAM-lets and L4 Cache, you can have LESS complex cpu dies because having GBs of "RAM-let" dies + extra L4 cache on the I/O die you would not NEED to make the CPUs registers and pipelines large to compensate for when CPUs are idling/waiting for data to calculate, so more die area will be freed up.
On top of that CXL is something AMD now supports (server at least, maybe TR), the version for extending RAM over PCIe (forgot the version name for it but AMD focused on memory first while iirc intel did not?)
We have already seen the first signs of RAM-lets with RDNA3 so that is a kinda given indicator that Zen 5 *might* be a total memory oriented architectural re-design, which I strongly believe (wish). What else would make Mike so excited than having 1GB+ HBM on die?
The SECOND consequence and kicker of having RAM-lets is that you do not need RAM on smaller systems like laptops! That is a DESIGN WIN by big proportions!
On desktop it means more than ever the ones that should be scared are the motherboard makers going forward. Motherboards in the future will look more lika a simpler server backplanes or PCIe switches with I/O (usb, nic audio). Going from "putting the CPU on to the motherboard" it will be more like "Attaching the motherboard to the CPU".
What could happen is that future motherboard will not have any I/O panels rather you buy a PCIe slot I/O bracket of your liking to your so called "motherboard" that is more like a backplane or PCIe switch.
Getting a bit ahead of myself but just showing what will be the consequences down the line by going to RAM-lets and CXL memory redesign.
A bit shocked only 7 day follow up!
Hope you can keep it coming, as long as it’s healthy for tou
I just want to say I'm so glad that you're back. You mentioned earlier that rough time you went through when you took a break. I remember when you announced that you can step in and wait was one of the saddest things I've heard the entire month. I love your videos I love your analysis I love your content I love your honesty. Everytime I see that you come out with the new video it's the highlight of my entire week.
looking forward to the radeon video, it amazes me how companies think they can lie on stage to everyone and no one will pay attention. Honesty goes a long way
How exactly did amd lie?
@@xFluing The selection of games they showed on stage had an average improvement over RDNA2 of 60%. The big benchmark averages show 42%. Now AMD was careful in saying "up to" in every claim. So it's legally not lying. But legally and morally are two different things.
@@andersjjensen every company does up to, regardless if it does or not.
@@MyndZero I know. But with RDNA2 AMD were bang on the money with their benchmark selection. Yes they said "Up to" for the best game they could find, but the overall presentation was truthful.
@@xFluing their performance figures were not at all what real world results were. 1.5, 1.6, and 1.7 performance uplifts that never happened
Who else listens to these more than once?
Yay :) part 2 - it's really good to hear you, Jim!
The Mike Clark "Father of Zen" interview is on TechTechPotato channel, so you can see Mike's happy smiles on the things Dr Ian is trying to loosen his tongue on.
Personally I see silicon designers being excited by the CPU arch internals, the ability to use 4nm and/or 3nm is likely a benefit of chiplet heterogeneity. Remember Tick-Tock?
It's risky to re-arch and port to a new node, so if Zen5 is about IPC & cleaning up cruft, while retaining the frequency gains of Zen4 then it makes sense.
Or the chiplet 2 CCD + IOD and Infinity Fabric even changing radically with the ground up redesign from "soup to nuts" as Mike says is perfectly possible.
Larger L2 with smaller local L3 but backed by a unified central L4 eliminating double hops between CCXs via IODs and managing the DRAM might be interesting.
The dual CCD x3D release with asymmetric caches could be a pipe cleaner for Zen5, introducing the software, gaining experience on a halo early adopter product, which isn't mainstream.
Those have been my thoughts as well. AMD could easily throw an L4 chiplet in there, or even integrate an L4 cache onto the IOD. That would eliminate the need for huge individual L3 caches on the dies, and potentially effectively kill the asymmetrical die setup. Such a setup would also probably fit well with a potential 8 Zen 5 + 16 Zen 5c design, so that the cache-reduced cores have access to a large cache pool anyway, even though it has increased latency (which wouldn't matter all that much for them). This gives me Intel Broadwell flashbacks. The underrated and very scarce 5775C was a beast in some applications due to its inclusion of an L4 cache, despite the numerous drawbacks it had from being on an early and bad 14nm process, like low clocks. The important thing is, AMD has so many alternatives available in their designs, that they have to mess up big time to come up with something less than very impressive. It's going to be an interesting generation in any case. Arrow Lake does look mighty interesting too, but it's gonna be going up against Zen 6 or Zen 5+, both of which would be further refinements of the Zen 5 designs. Intel is gonna have a very rough time, even if they don't downright lose.
We haven't seen 3 ccds and a io die yet though.. but they could be not the same from each other
@@959tolis626 Great response! It's really nice to read reference back to the EDRAM style chips which were desirable for gamers.
So I heard the IOD is actually the hottest part of Zen4, so that's the reason I spoke of an MCD for L4 which is analogous with the RDNA3 design choice.
Zen4 V-cache is still on 7nm, not even 6nm, and I can imagine cache coherency being simplified if the memory controller chiplet is managing L4, it can write-back to DRAM and fetch data from specific modules. You could imagine that scaling across more channels without having to have a huge IOD in EPYC/ThreadRipper chips.
I totally agree that the flexibility of chiplets is not recognised by everyone. Even Jim here seems to miss that the 4nm option for the new CCD is a result of the disintegration as 3nm CCD design can work in parallel targeted at the same IOD/MCD.
I feel that L4 intuitively is the correct answer to the double hop latency imposed by going across CCD boundaries and AMD Zen3 & Zen4 already implemented improvements to reduce the impact of cross CCX data fetching.
Now we must remember Zen5 is EPYC, mobile & desktop, so a seperate IOD could allow iGPU cache too, which might help accelerator functions.
There's marketing reasons to keep the consumer product aimed at games & creator workloads, with the beefiest quad channel memory & i/o being held back for EPYC/TR platforms.
@@RobBCactive Yup, same thinking here. Although I don't know how feasible an MCD style L4 chiplet would be from a packaging standpoint. Like, how do you actually match that to the CCDs? If there's one per CCD, it's useless (not to mention it sounds an awful lot like HBM). If it's one for each pair, then you have problems with Threadripper and EPYC. That's why I thought it'd have to be more centralized to make sense. But yes, I'm thinking the same thing, it effectively alleviates the double hop issue, and cuts back on the need for massive L3 caches. So, even though it would be expensive, I could see a potential SKU with increased L2 cache, little or no on die L3 with maybe stacked v-cache on top, then a centralized larger L4 cache to tie it all together with system memory. Now, with that said, I'm thinking AMD will probably end up changing their CPU package layout on AM5 anyway if they are to include accelerators, as those take up space as well. Thing is, I don't see them doing that for consumer/"gaming" CPUs anytime soon. Lastly, since you mentioned the iGPU, if they could beef that up a bit, I could see them leveraging it in a Ryzen + Radeon combo, where the iGPU could handle game functions to free up GPU resources, like maybe assist with AA or some postprocessing. It should be able to do that, as the grunt of the work on shading and lighting and textures would be on the dGPU. Not to mention they could use the iGPU to accelerate encoding/decoding of video, Quicksync style. The possibilities are literally endless. At this point, with the tech they have available, it's more a matter of what they think about and what makes financial sense, rather than what's possible.
PS : I don't know how much sense it would make for them to increase the core counts on the standard Zen 5 CCD by a lot. I somewhat expect them to utilize Zen 5c (or even Zen 4c, because why not?) as their second CCD and adopt an Intel style P+E core design, with their "E" cores being much more capable than Intel's. I mean, if I'm not wrong, Zen 4c cores support SMT, right? In that case, without increases in core counts, we could be looking at a 24 core (8P+16E)/48 thread CPU on AM5. Software support for this kind of CPU asymmetry has already been implemented for Intel's CPUs, so not much work to do there either. I think they'll be stupid if they don't at least consider the option, as Intel would again lose the multithreaded "crown" they've been holding with Raptor Lake.
Sorry for the long post. Cheers!
@@959tolis626 well you would put the LLMCD (Last Level Memory & Cache Die) chiplet to suit the main memory address and data lines but have Infinity Fabric links to the CCDs. It could include a compact 4c/8t efficiency core block, not intended for general applications but OS & low priority background processing from CPU over bus/main memory.
Conceptually the CCDs then assume fetch/store is offloaded to the L4MCD chiplet.
Similarly each CCD of 1 or 2 CCXs, has the CCX wide unified L2 cache according to the leak, meaning the LL is L3 not L4.
The IOD features an iGPU, Ryzen AI and other accelerators, whether they are best on a different chiplet or part of the same one, perhaps with much cache stacked on a cool running area of the chiplet.
The situation is NOT worse than the monster EPYC/TR IODs supporting 8 chiplets, but splitting the tasks lets the cache be on a cheap process node and it's the Infinity Fabric which allows chiplets to communicate.
If the IOD were seperate, it'd be up to 8xCCD + LLMCD + IOD making for 10 chiplets and the LLMCD could perhaps be using stacked V-cache on top of IOD functions.
However there could be shared V-cache per 2 memory channels like in RDNA3, if data belonging to an address range is ALWAYS in a particular part of LLMCD then it simplifies the cache coherency messaging, because each CCD just asks the LLMCD which knows if DRAM, itself or another CCD HAS the latest data.
great to hear from ya Jim! i've been out of the tech loop just keeping twitter in write only mode for my own sanity. and here you are with some great insight to keep me up to date again.
Zen 5 on 4nm and 3nm, could also mean that there could be a cheap 4 Core 4nm version. It could be a sucessor for Mendocino.
It could also mean that desktop will stay on 4nm while laptop goes to 3nm.
It could also mean that laptop and Server goes to 3nm where efficiency is king while desktop stays on 4nm.
There's alot of ways to interpret that slide.
Don't forget a possible 4c refresh too for mobile, they can do so much this time
They can easily take productivity and gaming crowns in the mobile space if they segment it correctly, high and low core counts on high and low power devices to get all possible market share.
By the time you get down to the 3nm process with how expensive it is a 4 core would fall below the value bell curve, Yields might be amazing but the dies would be so small you spend forever cutting the wafer and going through saws.
The most likely option is power-creep, instead of 4core and 4MB it'd be 6core and 12MB, the die cost isn't significantly higher (compared to the total BOM cost of building a system) but that extra 50% more power does allot for users, marketing and sales.
@@tomstech4390 OK, but an ADDITIONAL mature 4c/8t core block running at lower frequency in IID (or an MCD) might make a nice set of extra little truly E-cores that the OS has available for common tasks running at memory speed and don't need to wake up any of the main CCXs.
Edit: for clarity as the implication of parking the CCXs wasn't clear enough.
They can fit onto an MCD die with extra V-cache options, there's no need for the latest process or a seperate chiplet.
Just look at the common use of compact Zen2 in APUs like Steamdeck, Xbox and PlayStation.
@@RobBCactive yeah but that's last Gen stuff already showing it's weakness. The size, power usage, and low cost of new 4nm 8 core dies means nothing needs to be 4c anymore. No one wants 4c, that's useless. It won't exist, they might cut down an 8 to a 6 for yield reasons like the other guy said, and for segmentation.
Even today 8 cores is 300-400 dollars and is the ideal for gaming... It's not top tier so it's not "expensive" but it's not cheap either, and everyone knows it's plenty for gaming even for high end systems.
Next Gen, in a year from now, that may start to change, where 12 and 16c is the "value" 400 dollar gaming King, that's just as good at gaming as anything higher end, but the 8 core might become the new 6 core... The budget gaming option, while the 6 core becomes truly entry level. And hopefully more games actually benefit from more cores in 1-2 years.
You don't often make mistake and when you do, you hold your hands up and explain why, we can't ask any more of you. I was distraught in Oct 2021 when you said you were getting fed up of it, I would've understood if you wanted to take a break but I, for one, am happy you're still covering tech and that you find it interesting, Keep up the good work 👍
I have to say, being a long time member of this channel, i've firmly missed these deep dive videos! - Well done Jim, and as others have said, dont be too hard yourself, accurate enough with caveats is great! Glad you're back.
Good to see you back, hope to see you more frequent
Intel is in so much trouble right now that Pat has no other choice to be optimistic.
Pat once said the Intel returned to “unquestioned leadership” in the CPU market. Take his optimism with a grain of salt.
@@tringuyen7519 you should always take videos like this with a grain of salt. I thought that was a rule at this point?
TSMC has revamped its 3nm process. N3E supposedly yields much better than their older N3B process and volume production is set to start soon. SRAM density will be exactly the same as 5nm though.
Thank you. Your videos are among the few special gems for sure. May i ask if you could do a follow-up to a topic you touched a few years ago, one that forever have been a special interest to me. Speculative multithreading. Im dying to know more about when we will finally get it. Thanks again :)
Jim, I am glad that you are doing better again. I suspected that you were struggling with personal issues when you dropped the channel.
Nice to watch your videos again Jim!
The "catch you later" better not be another 4 months in the future.
Great work as always Jim
Never does an almost 33 Min video only feel Like 5 Mins with Jim and his Great deep dives !!!
The real questions are how long can Intel keep up the price dumping and how long can they hide a meek 10% gain.
10% boost using 30% more power LOL.
They got money to dump a little more, but the market is not happy with it.
If Meteor Lake uses TSMC 3nm for both the iGPU and CPU dies, why did Intel chose not to use Intel 4 process? What’s the point of the Intel 4 process?
Price dumping? What are you talking about? Where I live (Sweden) I can barely find a reason to buy Intel on price alone! And since AM5 and AMD in general is so incompetent and have to give free ram away just to make us buy there new CPU's? :) But not us Europe people. No we pay full price!
Maybe a 12600 - 13700k or whatever might make sense vs AMD stuff. But otherwise Intel parts cost far more then AMD and performer worse then AMD.
How long can Intel keep on paying dividend or whatever insanity going on right now at Intel? Without lowering there prices and becoming humbled by being shit compared to some glued together CPU's?
@@TheDiner50 Simple math to your rant. The 13700K and the 12900K are essentially the same exact processor and the 13700K is approximately 10% faster. A very minor upgrade in performance. There was no node change between the two and in fact the die on the 13700K is larger larger. Yet, the 13700K initial msrp was $200 less than the 12900K. Either they were way over charging for the 12900K (not likely) or they are dumping the 13700K to maintain market share. If they were a foreign company in the US that would be illegal. Unless you believe that Intel improved their manufacturing costs by 32%.
@@robertmyers6488 * Either they were way over charging for the 12900K (very likely) ...
Here, fixed it for you!
Thanks for blessing us with another video :)
Zen designs so far have used a ring bus of unknown topology (probably a bisected ring), that runs around the L3 area of a CCX. Intel has a long history with large ring bus CPUs, and I think their experience is that ring buses start to really suffer past 10-14 cores per ring. With that in mind, I would imagine that AMD would not go for a 16 core CCX, and instead opt for 10-12 cores, and a 3 CCD 30-36 core desktop part if they really need it. If not, then just 20 or 24 core.
They might go to a mesh topology, don't forget the famous butter- donut!
There's not a reason they can't put two CCX on a CCD again, the issue you're looking at is cross-CCX latency. Changing it to a mesh of CCX nodes instead of everything going back to the IOD might be possible.
12:10 thank you for writing down die prices as text in the calc
if 3nm isnt ready yet, then AMD is doing the right thing. Better to sell dependable and fast stuff even if its not bleeding edge tech every time.
By the time Zen 5 is coming out, 3nm is going to be ready. The first N3 (N3B) variant is ready now, it just sucks. It requires a ton of EUV layers, not great efficiency, performance increase, and is just bad. The end of this year N3E should be mass production ready, and it is better in every single way, including less EUV layers, faster, more efficient, and cheaper.
AMD has from the start of the Zen series been taking a conservative approach to using new nodes, they've discussed the strategy publicly in several interviews over the last few years. AMD has been prioritizing design strategies to overcome the slowdown of advantages from new nodes along with the increased costs, by the time AMD goes big with 3nm, it'll be much less costly with high yields.
WOW! Watched both parts and subbed!
Jim, 32c/64t CCD was not unreasonable for Zen5, Zen4c Sienna delivers precisely that with lower frequency lower L3 dense CCD cores.
A CCX of 8c/16t or with the CCD disabling the worst 2 cores for 14c/28t to mitigate thermal density seems possible design choices.
I could imagine the V-cache being re-architectured, 7nm on an MCD with CCDs eliminating the double hops from CCX to far CCX in a different CCD.
The question might be whether Zen5 will have 8c/16t of full power cores, backed by Zen4c like 16c/32t for those creator render benchmarks.
An asymmetric arch could even have a quad little 4c/8t compact cores for power savings as the OS is often doing memory bound tasks. CCD parking would allow the full CCD TDP to go to the fast performance 8c/16t in workloads which aren't embarrassingly parallelisable.
I know that it is a real term, but whenever I hear "embarrassingly parallelisable" I imagine someone trying to make his workload run well on a dualcore, followed by a coffee mug shattering on the floor. "Oh God. I could have run this on *three* threads this whole time."
@@klobiforpresident2254 😁😁 well some things break down into small chunks .. most complicated code doesn't, you end up with dependencies and finding mitigations is really hard
I meant 32c/64t dual CCD was not unreasonable for Zen5, Sienna brings 16c/32t per CCX/CCD.
can't wait for your RTG video
Back when Lisa Su revealed 3D cache she talked about the benefit just slapping it on an existing product, but was hyping the potential when the CPU was designed around it. I thought that meant Zen 4, but it looks like it may be Zen 5.
Thanks for the video.
At 14:16 in the video, I had a thought L3 cache not scaling, then remove it from the die and add L3 as 3DV cache to all chips.
Now you have room on the die to add more cores, 16 cores on a smaller 3mn process, and L3 as 3DV cache. Just a thought.
50% yields does not even make a dent in chiplets that can be sold. Perfect 16 cores go to epic and HEDT, 14 cores 12 cores and so one get move to Ryzen, the damage chiplets just get moved down the product stack. AMD has in the past been good at making a bad process node work to there advantage.
Intel was never and never will be dead and I am on an all AMD rig right now. I have a 5900X paired with a 6800XT. And I am saying that.. Intel has mind share.. Even on Dell, HP, Lenovo, and ACER PC's you hear that Intel Jingle at the end of every Commercial.. I am a Resi Cable Tech, and I go in homes for a living, and trust me most people don't even know there's a Company called AMD and that they make CPU's and GPU's.. Seriously the only people who even know about AMD products are the ones who PC game/Edit or they bought an AMD an AMD PC or Laptop because the one sales person at the Bestbuy knows their shite.. I loved what Intel did with the P and E cores.. But they are taking it to far with the E cores and Power right now.. If it takes 350 watts to beat a 200 watt AMD part they can keep it.. I am all about power per watt.. I even run my GPU with the fans off on the ECO BIOS. Oh and I do love having a dual BIOS, that's a great feature for GPU's.. But anyway Intel is huge and they are everywhere.. Their Old Parts are still fast..
You may have a point, but I'm seeing more and more office PCs with AMD. I think AMD is making serious inroads there. I think they need a stronger advertising arm (why the consoles don't display an AMD logo is beyond me), but they are winning where it matters: High-volume enterprise computers.
@@prycenewberg3976 I agree They need to work on showing the public who they are and what everyday products they are in..
you are right... a friend wanted a laptop... and he saw a second hand one for about 500$... overpriced ofc.
and i recommended a new laptop, a lot better than that 4-5y old one, for 450$... and it is on AMD 7520U... and his response at some point was... but isn't that 6 y old intel cpu better?
the majority of people are so blind to the things that happen in this sector, and for advice they go to the shop keepers... that focus on profit, and if you like intel, why not, give the man what he deserves. how napoleon hill said it" opinions is the cheapest commodity in the world"
depends how you define dead.
I personally wouldn't run electronics without a fan on
This video explains why a lot of people didn't feel the need to go from Zen 3 to Zen 4, Being that Zen 4 is just a shrunk down version of 3 with slightly more L2 and L3 Cache which is what really made the difference in IPC along with Clock speeds.. Like if Zen 3 ran at 5.8Ghz too and held a Base clock above 4.6Ghz it would have number's similar to Zen 4 too.. I also see now why they had too go to a new socket for more power.. I'll be ready for Zen 5 when it comes out along with Navi 4 too..
Glad you're back, sir. Mistakes will be made, owning and learning from them is all that can be done, and your track record bears mistakes easily, imo. =) Like everyone else, I definitely look forward to hearing your thoughts on RTG. =D
I often wonder where Intel would be right now if the Intel board backed Jim Keller fully when he was there so that he stayed rather than decided / was forced to leave? If they kicked Bob Swan out earlier and gave the job to Jim??
Man, Jim as the CEO... different world. 😃
Keller is now CTO of his own AI start up. There's now a lot of attention directed at AI related companies, and buying a company is simpler and faster than rolling your own from scratch. Maybe Intel will one day make an offer that no one can refuse which brings Jim back to Intel. Perhaps AMD buys Jim's company out and he's back at AMD again. Maybe Nvidia buys the company out. Perhaps Tesla? The man has options.
@@geekinasuit8333 What I found interesting about Jim Keller's startup is that they might make AI chiplets, to be potentially integrated in AMD and/or Intel products, that he may have had a hand in making chiplet based.
Dense cores on the early N3 processes sounds logical to me. The process is designed for smartphones first, then altered to high performance later, usually.
Thank you my well informed Scots man! I respect your humility and appreciate your effort! 🎉
Hi Jim, your initial assumptions about an L3-less Zen5 CCD is more or less what I too naively expected. It'll be interesting to see when they go down that route - because it's almost bound to happen at some point.
I'm a simple man, I hear a scottish tech youtuber say "all right guys, how's it goin?" and I instantly leave a like 👍
Last few videos have been... Epic!!
***Epyc
RTG cant seem to catch a break since GCN i dont know how to think about it, it feels like they are hitting a brick wall and i want to say its just bad luck but how long can this go on for
If AMD went 100% stacked for the L3 even at 7nm, that would have more or less allowed to fit 16 cores in the same footprint. So they could have made a 16 core 64 mb L3 cache like a couple of years ago.
Intel is in serious trouble if they need to rely on TSMC for their CPU cores. This means their own fabs will be vacant. They are trying to sell that capacity as an IDM, but their purchase of Tower Semiconductor isn't even approved yet which is the key of that puzzle. And they are already bleeding cash.
How can Intel sell fab space to anyone who is also competing with Intel in the CPU space? Intel will never get AMD as a client. ARM CPU's also eats away at Intel's marker share, so that's a tough call as well. Same with the GPU space now that Intel appears to be trying to enter that sector. IDM is concept that's in a conflict of interest position which will be a drag on much needed adoption. What Intel should do, is what everyone else has already done long ago, which is to split the fab business from the design business. One exception is Samsung, but Samsung is in a very unusual situation that makes it possible to do almost everything.
Pretty much. Intel also can't afford to buy TSMC wafers. It's just another expense decreasing their margins.
I would have to imagine that the people at AMD are smart enough to not put ALL their eggs in a single basket(3 nm). At the same time, you would hope that Intel has learned just the tiniest bit of humility.
the problem is intel underestimating the complexity of making a modern product. not just manufacturing but design and DTCO. they started too many projects and had design principles not aligned with the exponential design/verification/validation costs, while not executing to the level of detail necessary.
I don’t think they are underestimate how complex these products are, they are just not taking advantage of the biggest advantage of chiplets/tiles.
How I put it is like this:
AMD is making products from chiplets.
Intel is making chiplets for A product.
Meteor Lake had 3 compute tiles that we know of. 8+16, 6+16, and 6+8. That is the same amount of dies that the entire of base Zen 4 using a for server, desktop, and laptop. Zen 4 CCD and an IOD for Server and laptop/desktop.
@@benc3825 you also need to remember that intel is on a completely different scale than AMD, so their approach isn't necessarily wrong from that perspective. i think the issues lie elsewhere.
@@elon6131 No, it is 1000% wrong. They honestly never had the money to do 8 tiles for a single product line, and this has been years in the making. This was a suicidal decision, R&D cost per die is in the hundreds of millions, this isn’t new.
500 million for a 5nm die
300 million for a 7nm die
175 million for a 10nm die
These aren’t new costs, these are very close to per die costs
@@benc3825 it’s not quite that simple, while these are the base costs, you can re-use 80-90% of the work (verification costs are what’s ballooning), making subsequent iterations of the same IP significantly cheaper. So while that first design is indeed quite expensive, doing the same thing but with half the cores is not.
I love hearing about the bleeding edge of new tech. At least tech for the commercial public sector anyway
Another combo that gets to 160 cores is 16C×8 + 8C×4: the higher density cloud cores plus some lower density high performance cores.
Great video! 😉
Another great video!
Kinda funny how AMDs competitors have been one-upping them with increasingly desparate moves. Nvidia having to jump a whole process to make sure they stay in the lead, Intel glueing dies together and hitting a power limit. Intel and NV may produce better performing products, albeit with a number of caveats, but they are running out of moves to make to stay ahead tbh. Given a process leap to 4nm, RDNA 3 vs Lovelace is an Apples to Oranges situation but really NV has that 4nm chip fully tapped out with the 4090, I really don't know how they could make a competitor to a 4nm RDNA 3 chip. Similar situation with Intel, the watt/perf is just a complete wash to AMD yet Intel still hangs in there for gaming (better memory controller) but how much further can Intel really keep pushing this if they are already hitting temp and power limits meanwhile AMD is putting out a 65W 7900. Can't lie though RDNA3 was very underwhelming, all of the leaks prior to launch were saying 3GHz and better than 4090 and we got exactly the opposite, an underperforming RDNA 3 and Nvidia's greatest GPU since the 1080ti. RDNA2 was great and AMD are really putting the pressure on Intel in CPUs but I'd really love for them to pull thier shit together in GPUs before Intel overtakes them there.
I dont really see it as desperation at all, I don't even think Nvidia even cares about what Radeon does. They never talk about them.
Nvidias RTX 4000 isn't even a real 4Nm node though. It's still 5nm enhanced plus they have rt and tensor cores in their silicon.
Nvidia was able to match and surpass AMD last gen on raster and blow them away in ray tracing while also having tensor cores as well taking up space in their silicon and they were on a worse node, Samsung 8nm.
Intel's cpu's this gen are pretty good though, power hungry but still solid performers. I'd say Intel is more worried on the server side than us diyers
Ever since i saw the Sandy Bridge die shot I was thinking "they should move all this cache off to another process, look at how much space it takes up!" I didn't understand latency penalties 10 years ago, and that it was not suitable to change the design back then.
12:45 but why are you punching 50% yield into the calc? I thought fabs measure yield using some microscopic ARM Cortex.
14:45 again why 0.5 if the die size changed?
To show worst case scenario and the reasons why zen 5 may be mixed nodes. It gives perspective on wafer cost, yields, etc.
22:13 The slide doesn't say Arrowlake is targetting Apple. It's targetting OEMs who want to compete against Apple in the "ultrabook"/ premium laptop segment
May I ask why when you were making die prices comparisons with varying yield values, you used 10000 per wafer on zen 5 and 17000 for zen 4? Did wafer prices drop that much? (edit: Correcting grammatical mistakes)
They drop over time and each new node increases the price. 7-5 was a very large increase.
@@adoredtv Tanks for replying. I rewatched that part and now I see I mixed up zen 3, 4 and 5 wafer prices. Sorry for wasting your time.
That 16c zen5c sounds like something laptops could use. Now the 7045 has two chiplets to get 16 cores, and that makes them drain battery and brings latency. Going up from 8 cores on thin and light would be nice.
The best content as always❤
All your CPUs are belong to us.
Zen 4 underwhelming? It was a bigger increase over Zen 3 than Zen 3 over Zen 2 was
Any more thoughts or ideas about The Cosmos?
Not all workloads benefit from the expanded L3 though. I really don't think vcache should be standard unless they can add it with having absolutely no effect on the clocks, which just isnt realistic. The interconnect between the cache layers and the increase in physical distance to the furthest banks of the cache is absolutely going to affect clocks. It may be able to be mitigated with future efforts, but the effct will never be a 0% clock speed hit. It just cannot happen. Maybe if they can disconnect the cache clocks from the logic clocks, but I fail to see how that would even work.
I'm still waiting for the 128c "Starship" (old codename), only 96c to date...
I wish they'd just go all in on vcache and drop the regular. There's seemingly no reason to buy the base models when you know vcache is coming it just beats them hands down on desktop. But on the flagship/muilti CCD chips they need to do two vcache CCDs and not one.
Imagine a binned 12-16 core with lots of 3D v-cache, Intel needs to step up their game
@Noodles1922 they have Foveros lined up 😅
cant stack 3d cache like that.... and there already having issues with heat at 6-8 cores.......
@Noodles exactly, that's basics now
@@shanekhiu9884 But is it good enough? I'll believe it when I see it.
@@EnemyDwarf-TTV what do you mean by that? AFAR 5800x3D and 7950x3d are running fine, very power efficient too.
With regards to ARL-P schedules. It should be noted your slide appears to be from March 2021 (2 years ago) with a planned PRQ (launch qualification) of WW33'23 which means a Q4'23 launch. However, we don't really know how much buffer they had on top of that as a "drive-to" schedule is typically considered 60% confidence (at least it was when I was managing products there). Also note, the decision to go to TSMC could NOT have been Pat's as he had just become CEO when this slide was released. Do you remember the leaks that Bob Swan was considering to use TSMC back before Pat replacd him. Well, clearly this slide and schedule are a result of that.
another reckoning is due? XD it just never ends with radeon, cant wait for that video.
Amd has zen 4 3d, Zen 4, Zen 4c cores.
The Zen chiplets dual die were never symmetrical. Huge differences in 3900 series, less in 5900, even less in 7900. I think low-end, console & mobile and might actually use some 4c cores, after phoenix is is released...
Future ccx is likely to expand to 12 or 16 or use 8 full core & 8c- cores
I'm thinking about 4c only parts for productivity and 4(3d) + 4c 24 cores gaming/productivity beast.
Time for a less than 15w beast Apu that can do anything too
You really got me thinking when you mentioned AMD might move the whole of the L3 cache of the die and add it as vcache. This technique can also be applied and probably with multiple layers on the IO die forming a L4 victim cache equally accessible by all chiplets. Since the IO die doesn't get as hot as the compute dies, multiple layers of vcache might be possible. If this is the case I wonder how big the L4 can become and how fast it might be. Can it be as large as a full gigabyte? How much impact would this have on memory intensive workloads with a latency way below regular RAM. And how much would it add to the cost of such IO die?
And please continue to elaborate the enthousiasts with your view on computer tech. No one else is at your level of analysis.
All these roadmaps blur things. If you consider AMD Phoenix 2 as a first foray into big little architecture, AMD has 3 solutions up it's sleeve.
1. Regular Zen cores.
2. 3d vcache Zen cores
3. New little cores that are being experimented with.
Now they will be able to mix and match these to fit the market needs, all with best power consumption. Intel will have a hard time competing in a way that doesn't demage their margins.
Jim is definitely one of the Voyager probes of PC leaks. We don't hear him often but when we do, he always delivers many wonders 🔥🚀
Have a great weekend ahead and keep it up the great job
Not dead but got so much else going on. AI is coming!
What I really want next generation with Zen 5 is to see them mixing up dies on the AM5 platform.
Basically. Instead of just 1 or 2 Zen 5 dies, have a Zen 5 die, a Zen 5c die and/or a Zen 5vcache die.
If you think about it, if we assume that AMD sticks to the 3 die design (though they might have room for four).
You could put a zen 5vcache die and a zen 5c die together. Ending up in a big/little situation where they have smaller, efficient, zen cores running the computer as a whole
And big, powerful, cache happy cores for gaming.
And if we happen to get the option to have a third core die in am5, we could see a doubling of performance cores, either in x3d or in regular zen5 cores.
There are a lot of options here. I am not sure though if it requires a new IO die, but would be interesting.
Would be even more interesting if they could start putting HBM on package... but that's probably me just having pipe dreams now.
We are already seeing this. Little phoenix leaked with 2 Zen 4 cores and 4 Zen 4c cores. 12 threads but with 8 of those being very efficient and with very little cache. Zen 5 will be indeed mixing and matching
@@VideogamesAsArt From my understanding Phoenix is monolithic, and little phoenix most likely will be as well. I was referring more to chiplet based CPU's with a mix and match of different types of cores.
@@Sindalis1 true! But if different core types are mixed in the same CPU, it can be done in both a monolithic and a chiplet based approach! The only thing that prevents it is software (that would correctly allocate work in the best cores depending on the type)
Not the first time I've yelled, "Damn you Bergamot!" XD
Gelsinger would say that though to keep stock from crashing
Yep. Also, CEOs are carefully coached by lawyers when they make public statements. The statements are carefully worded so it's virtually impossible to sue them, even if they turn out to be misleading.
I could see AL-P, -H, and data center being produced by TSMC, but the rest of the lineup being produced in house at Intel.
I don’t think when larger consumer more core per dies Zen comes, whether that be zen 5 or 6, it’ll be s full 16 cores per day. More likely to be 10,12 or 14. I have w feeling they’ll start adding a second die crammed full of E cores as an option by then too. Prob Zen6 tbh. Pure speculation in my part but makes sense.
I saw somewhere that vcache is still on 7nm due to the scaling issues, it was just redesigned for Zen4 TSVs.
If that is the case, for Zen5 should be on 6nm and much cheaper. It would actually be cool.
AMD has been launching on N-1 nodes for a while. Apple usually pays for top nodes and AMD wants the stability and price of a proven process instead.
27:50 When was the last time Intel had to cancel multiple hundred million dollar projects and even go far as cancel sponsored ones in one year!?
All because the competition has shown them to passed them in couple years, Pat is bluffing and will take that risk and try to make the delay as short as he can.
So if I understand this correct. At this point AMD desktop/laptop and server will use different architecture some time in near future.
also VC die can be 5 or 7nm
Is this an iron dwarf reading to us?
Exciting
Intel 10nm is superior to TSMC 7nm in terms of transistor density.
The naming scheme TSMC uses for their process nodes is BS.
Information-gathering and information-processing ❤
intel is losing massive mkt share esp in server segment - this is unprecedented and ongoing #facts
If Zen5 die cost similar to Zen5c I think AMD should do mix on desktop. Even for winning in benchmarks.
Or... 3nm Zen4 CCD + 4nm L3-cache?
It's Diaper Wafer Time! (this needs to be a T-Shirt)
If they put the main cores on 4nm, they can't switch to 3nm in a later refresh. 4nm is a derivative of 5nm, so they'd have to tape out a completely new design for 3nm wouldn't they? It would make more sense build the new core on 3nm, and use Zen 4C for the dense cores, as that's already designed for 5nm, and can therefore be ported to 4nm without hassle. There's no benefit to designing the main cores for a dead end node.
Ok, guilty, who else hit the like as soon as you hear the legend's voice.
Me too.
Not me
@@djAmored Looking at your youtube channel, ya a gamer, not a technophobe, so you are forgiven 🙂
Always
Duh!
There is the last option: Zen 5 Desktop is 8 core CCDs on N3 with an L2 cache increase but not very much L3 (say 16MB) for their mainstream non-X variants and 8 cores with 96MB N4 V-Cache for their enthusiast X SKUs. This obviously assumes they're ditching the X3D moniker and ditch the hybrid V-Cache/Regular CCD approach of Zen 4. This could make sense if they're putting the cache chiplet on the bottom and aren't suffering any clock speed reductions. And it would put them in a better position to go for market share at the lower end (corporate fleets of quad cores and other "boring" machines). The problem for AMD is that their non-X SKUs are so good that people just start buying those as soon as they come out, and this approach would naturally segment that while also giving AMD the cost saving to match.
16 cores per fully functional CCX would be sensible, but designing servers around an average of 14 working cores per CCX means they can increase yield. They'd just need to find the right combination of CCX dies to hit the average. Got 10 16 core CCXs? Then you still have 4 die spaces left to fill the rest, which only needs an average of 9 working cores per CCX to work.
I honestly am pretty impressed Intel has been able to remain competitive. Sure they have had tons of missteps but server though way too expensive (Sapphire rapids) if priced right would be kinda competitive
13th gen laptop is pretty darn good next to a cheaper zen4 laptop CPU
I think it is pretty amazing that laptop high end for AMD and Intel beat last Gen high-end desktops in most workloads.
Monolithic intel designs chips cant be "priced right" because the yields are terrible
But Intel did not remain competitive on the most important category: server.
Benchmarks shows that a 56 core Sapphire Rapids burns the same power as a 96 core Epyc Genoa. Only people with more money than brains buy Intel.
Legend
How much better would Zen be if they are made as Monolithic?
Consider the chip sizes are so small these days, is there still a reason for single CCD SKUs to be made as a seperate 70mm^2 chiplet? The cost savings are peanuts, and none of it is being passed down to consumers. The memory and fabric controllers have 20W phantom power draw and over a 5 year life cycle this adds up to £200 as electricity bill for the end user. And I speculate that having a fabric link will more or less decrease performance as well.
Man the UK has insane electricity prices
This won't work in the server market. The advantage of chiplets is that you can use the came cores in both entry level desktop and high end servers, and the only difference is your io dies.
@@badass6300 We've been successfully remodelled after corporate hell land USA, except without the benefits of being the evil empire itself
They'd have better performance, sure, but they'd also be a LOT more expensive.
Think about it, what is the memory controller power consumption for SPR? We don’t really know because the memory controller aren’t separate from the cores. For all we know, the 20W could be less that SPR’s, also, it’s not like SPR doesn’t use a lot more power for a given performance.
Intel finally starting to get its act back together would be good news. Having had some real competition in the market to push things forward and not have endless refreshes of the same clearly accelerated development quite a bit. But that only works if the companies involved remain large enough to continue competing. And it was starting to look like AMD might end up eventually pushing Intel out of Servers, one of the bigger money makers, if they kept up messing up like they have been.
So hopefully the upcoming generations of hardware will indeed be a lot better performance wise.
Chip manufacturing is not even peaked. Consider the right to repair and technologies designed to stop repairs - every component has a detectable ID which inhibits exchange, repair, replacement or modification via software interaction between components. Farm Machinery, Cellphones, Laptops, Vehicles. Soon it will be home appliances, tools etc.
11:00 - in case you didn't know, you can still use the CALYtech calculator over on the internet archive.
18:00 - once you do the maths, it's hardly surprising is it. even on N3, you'd need to sacrifice too much per-core performance for 16c to make any sense on desktop. your argument of "it's already been 3 years of 8c CCXs" falls flat on its face because that's just not how things work here. we're still going to be stuck on 8c for a while, because that's what happens when process nodes stop scaling quite so well. that's part of the reason intel stuck with quad cores for so long with the demise of dennard scaling (see how well that lines up..). i'm sure we'll get there eventually, but all the 16c CCX rumours that keep popping up every gen are kind of ridiculous. cores take up space, and bigger cores are still better than more cores on desktop.
Not much to say this time it seems. guess we'll see how it goes for intel. really hoping for them to work out their process nodes and get back on track. samsung's efforts are interesting too, but they haven't had much success.. uhh, ever?
sound is bad for some reason, sounds so flat
If AMD want's to start off Zen 5 with non v-cache dies, that's fine but I think they should limit the skus to just the higher core count parts (Ryzen 9s). With the release of Zen 4 3D, now anyone who was interested in Zen 5 for gaming, will just end up waiting for the 3D parts anyways. Why buy a Zen 5 Ryzen 7 when you can wait about half a year for the 3D version for not that much more money but significantly better performance?