RISC-V Logisim ALU

Learn about the RISC-V instruction set architecture by building hardware. In this video, I use Logisim to build an ALU (arithmetic logic unit) that will eventually be incorporated into an RV32I CPU that can be synthesized on to an FPGA.
There are a number of resources that I recommend you study as you go on this journey with me:
RISC-V Green Sheet: inst.eecs.berkeley.edu/~cs61c...
Design of the RISC-V Instruction Set Architecture: digitalassets.lib.berkeley.ed...
Great Ideas in Computer Architecture (week 2 and 4): inst.eecs.berkeley.edu/~cs61c...
Other helpful resources:
Online RISC-V assembler: riscvasm.lucasteske.dev
Logisim Evolution: github.com/logisim-evolution/...

[@ajax123z]

This is really good content. Keep it up dude.
Honestly kinda crazy that you only have 200 subs. The quality of your videos is just so much better than mine. The youtube algorithm be just hatin sometimes.

[@chuckbenedict7235]

Thanks for the kind words. My last series on the Hack CPU was a limited niche. I am not surprised at the limited uptake to date. RISC-V has broader appeal. So I expect the channel will grow. Or not. I do this because it helps reinforce my learning, with the hope that others will benefit. I do have bigger plans for this series...from building a compiler, to application of machine learning to Logisim. Cheers.

[@ajax123z]

@chuckbenedict7235 I'll definitely watch your risc-v series as you make it.
I started learning about computers about a year ago, and I was surprised by that lack of detailed how-to videos. I, too, have made quite a few logic related and cpu building videos in the hopes of making it easier to learn for other people who get into computer building.