Video

great video!

I wonder how I can practice UVM and systemverilog at home? What programs do I need? Is there any free program I can use?

It's not clear why we need to record tranactions.

Thank u

Thank you sir

Hi John, reg2bjs doesn't work for me, can you tell me what could be the cause of the problem in general? Thanks

Great Lecture

Today, open source UVM register model generators are available: (1) PeakRDL using SystemRDL 2.0. (2) the Open-Register-Design-Tool (ORDT) using SystemRDL 1.0. SystemRDL is a powerful way to describe register models in a human readable way. Those models can then be used by generators to create documentation, UVM register layer models, C++ hardware abstraction layers, and so on.

Very nice series, thank you, enjoying it. However what's the value of having get_type_name() as a tag? I would recommend to use more meaningful tags, related to classification of messages or errors.

Very good refresher, appreciate you putting some time into it! Thank you

Nice

Thank you for this video because I got to know inner level engineering of register layer. The explanation was fantastic. Once again thanks

Everywhere it is mentioned that UVM sequence is a collection of sequence items.So suppose I have 2 sequence items ,one for write , one for read..does this mean a single sequence can have both the sequence items..in all examples there s one sequence for one sequence items..then how is sequence a collection of sequence items??

I learnt phase jumping from this video. 49:00

Thoroughly understood the overall system. I have been learning the languages without knowing how does it play role at system level. Thank you for making this video.

Thank you so much for this wonderful explanation of this topic which has been haunting me for quite a time now. Now I feel confident with TLM connections in UVM!

what is TLM?

can you tell me what a SystemC can do, and SystemVerilog can't ?

Awesome explanation!!

Thank you for the video! A Question: Why do we get the config inside the environment class and then setting them back to the configuration database so as to be retrieved inside each agent? Why did we not retrieve them in one step (From top_level module to agent, no need to get inside environment)? Thanks, Ahmed

The best explanation of UVM I could find, thank you.

For new learners here, we have already imported the uvm package inside of my_pkg, yet when we import my_pkg in top module, we are again importing uvm_pkg eventhough it was imported in my_pkg itself. Why is that? Why not just import my_pkg and call it a day?

Thank you John for this informative and easy to understand video on UVM!!

Here is my method which I think is a bit more intuitive. I can then place any number of variables within this struct. and since this is a struct you can use it with uvm_config_db::set and get easily. In future when we want to add more parameters we can simply modify the base struct my_param_t. here is my approach: typedef struct packed { unsigned int AWIDTH; unsigned int DWIDTH; .. .. } my_param_struct_t; Create a default struct as parameter: parameter my_param_struct_t default_params = '{ AWIDTH: 16, DWIDTH: 64 }; now simply parameterize all required uvm classes as well interface with this struct parameter and assign a default value. interface my_if #(parameter my_param_struct_t my_if_param=default_params) (input clk, input reset); endinterface class my_driver #(parameter my_param_struct_t my_driver_param=default_params) extends uvm_agent; virtual my_if#(my_driver_param) m_vif endclass parameter my_param_struct_t params_256bit = '{ AWIDTH: 16, DWIDTH: 256 }; module tb_top; my_if#(params_256bit) m_ifA(clk,rst); initial begin uvm_config_db#(virtual my_if#(params_256bit))::set(null, "*", "if_A", m_ifA) end endmodule Done. now we created a parameterized interface in tb_top with an entirely new struct params_256bit and passed it with uvm_config_db to the driver whereas the driver. It works because parameterization type is essentially same which is "my_param_struct_t"

love it!👍

Bro it's killing my eyes what is this compression

When you say choice of physical interface, are you referring to the communication protocol?

Hi John , am very delighted to listen to your explanation as its very easy to understand the concept with code. It would be really helpful if you have a explanation video on RAL model(adapters,predictor,reg write/read with RAL model) with the code. Thanks in advance John.

John, thanks for the very enrich and clear video. one point that was missed here is how you override agent config fields from higher hirarchy, for example at agent configuration i have many checkers knobs enable/disable. when i upload an reuse environment in higher hirearchy i'd like to disables some checkers or the same for collecting coverage. how it done by this way you choose to implemnt configuration? thanks

I know this video is 10 years old, but I found it really nice to watch now that I'm doing a masters degree and need to learn SystemVerilog, and don't know much about it, while coming from VHDL. Thanks, man.

Thanks your videos, can I ask about the topics are needed from c++ to be fully covered/understood to continue in SystemC and TLM2.0 ?

Absolutely excellent highlevel UVM overview. This vid should have more views!

thanks for making such videos

$TLM to moon 🚀 🤣🤣🤣🤣🤣🤣🤣🤣🤣🤣🤣🤣🤣

Can we convert UVC which is written in system Verilog to system c, any suggestion will be helpful thank you?

Great uvm summary! Thanks a lot.

navigation techniques ,key board short cuts please explain

great video.

Excellent video. One minor thing for newbies that took me a while to realize: 'imp' stands for 'implementation', and has nothing to do with 'import'.

So, much informative. Thankyou..!!

Very nice video John. But, how does one obtain a reference model?

its a nice trick, but there is something missing in the explanation and also in the online article. how can the instance of the concrete class inside the interface access the particular instance of the parameterized interface? i understand the concrete class is inside the scope of the interface and that allows it to access its variables, but the two instances are linked together?

17:00

10:00

5:30

6:26

Thank you this was very useful information!

What is the function of seq.randomize() ?

Excellent videos to get a strong grip on the fundamentals

Hii John this video is really great👍 I request you if you can make video about scope resolution operators