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Codasip
Germany
Registrace 9. 05. 2017
Codasip is a processor solutions company which helps developers to differentiate their products. We are Europe’s leading RISC-V company with a global presence. Billions of chips already use our technology.
In today’s technology market, differentiation is everything. The difference between success and failure. And, in chip design, this difference is quite literally wafer thin. With increasing transistor costs, your developers can no longer rely on semiconductor scaling and legacy processors to achieve your goals. The only way forward is to implement custom compute with designs tailored to your applications.
We deliver custom compute through the combination of the open RISC-V ISA, Codasip Studio processor design automation and high-quality processor IP. Our innovative approach lets you easily customize and differentiate your designs. You can develop high-performing, and game-changing products that are truly transformational.
In today’s technology market, differentiation is everything. The difference between success and failure. And, in chip design, this difference is quite literally wafer thin. With increasing transistor costs, your developers can no longer rely on semiconductor scaling and legacy processors to achieve your goals. The only way forward is to implement custom compute with designs tailored to your applications.
We deliver custom compute through the combination of the open RISC-V ISA, Codasip Studio processor design automation and high-quality processor IP. Our innovative approach lets you easily customize and differentiate your designs. You can develop high-performing, and game-changing products that are truly transformational.
With great power comes great responsibility - Customizing your processor with verification in mind
Codasip Studio Product Manager Filip Benna discusses how to customize your processor whilst keeping verification in mind. This talk was given at the 61st Design Automation Conference.
For years, Codasip Studio has been the go-to toolset for generating both RTL and software development tools from a single processor model. The latest version, Codasip Studio Fusion, enhances this core capability and introduces a layer of segmentation. It allows you to configure the core from predefined options, create custom instructions within set parameters, or design with complete freedom.
For years, Codasip Studio has been the go-to toolset for generating both RTL and software development tools from a single processor model. The latest version, Codasip Studio Fusion, enhances this core capability and introduces a layer of segmentation. It allows you to configure the core from predefined options, create custom instructions within set parameters, or design with complete freedom.
zhlédnutí: 117
Video
A short overview: Codasip Studio Compiler
zhlédnutí 33Před měsícem
CTO Zdenek Prikryl gives a quick overview of the Compiler capabilities of Codasip Studio
A short overview: Codasip Studio Profiler
zhlédnutí 34Před měsícem
CTO Zdenek Prikryl gives a quick overview of the Profiler within Codasip Studio
A short overview: How to relate generated RTL back to CodAL
zhlédnutí 51Před měsícem
A short overview: How to relate generated RTL back to CodAL
A short overview: Getting started with Codasip Studio & CodAL
zhlédnutí 67Před měsícem
A short overview: Getting started with Codasip Studio & CodAL
DAC Demo: AI Inference for anomaly detection on an embedded RISC-V core
zhlédnutí 166Před měsícem
Solutions architect Troy Jones showcases the latest Codasip demo live from DAC 2024.
How do vector length agnostic architectures work?
zhlédnutí 347Před 3 měsíci
A short overview of the similarities and differences between SIMD and Vector approaches, and a description of how the RISC-V Vector code is portable between machines of different Vector lengths.
Toby Wenman talks about Vector load/store segment instructions
zhlédnutí 163Před 3 měsíci
Toby Wenman talks about Vector load/store segment instructions
Codasip Demo - Accelerated DSP on a Customized RISC-V Core
zhlédnutí 144Před 3 měsíci
Alexey Shchekin demonstrates the Codasip L31 (3-stage 32-bit RISC-V) processor on FPGA that runs several DSP algorithms: FIR filtering, FFT, Viterbi decoding. The processor is customized with Codasip Studio and enhanced with hardware accelerators that improve the performance of these DSP algorithms.
Codasip at Embedded World 2024 - meet our partners
zhlédnutí 195Před 3 měsíci
Codasip at Embedded World 2024 - meet our partners
CHERI Demo at Embedded World 2024
zhlédnutí 124Před 3 měsíci
Andrew Lindsay demonstrates an example of our award winning CHERI implementation at Embedded World 2024
Carl Shaw - CHERI protection & software
zhlédnutí 169Před 4 měsíci
Carl Shaw - CHERI protection & software
Carl Shaw - Compartmentalization CHERI
zhlédnutí 78Před 4 měsíci
Carl Shaw - Compartmentalization CHERI
Ben Fletcher - CPU performance modelling
zhlédnutí 408Před 4 měsíci
Ben Fletcher - CPU performance modelling
Carl Shaw - What is CHERI and why is it necessary?
zhlédnutí 279Před 4 měsíci
Carl Shaw - What is CHERI and why is it necessary?
Jamie Melling - Understanding RISC-V virtual memory
zhlédnutí 591Před 4 měsíci
Jamie Melling - Understanding RISC-V virtual memory
Tariq Kurd - Efficiently managing tagged memory for RISC-V
zhlédnutí 157Před 4 měsíci
Tariq Kurd - Efficiently managing tagged memory for RISC-V
Codasip at RISC-V Summit US 2023 - Day 2
zhlédnutí 67Před 8 měsíci
Codasip at RISC-V Summit US 2023 - Day 2
Codasip at RISC-V Summit US 2023 - Day 1
zhlédnutí 63Před 8 měsíci
Codasip at RISC-V Summit US 2023 - Day 1
Codasip at Design Automation Conference 2023 DAC
zhlédnutí 137Před rokem
Codasip at Design Automation Conference 2023 DAC
RISC-V customization demo: AI-based image denoising
zhlédnutí 195Před rokem
RISC-V customization demo: AI-based image denoising
RISC-V Summit Europe 2023 - Codasip summary
zhlédnutí 127Před rokem
RISC-V Summit Europe 2023 - Codasip summary
Architecting ambitions with custom compute #ew23 #embeddedworld
zhlédnutí 475Před rokem
Architecting ambitions with custom compute #ew23 #embeddedworld