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flip flops | Characteristic equations | STLD | Lec-121
STLD : Switching Theory and Logic Design
Characteristic equations of flip flops
SR, JK, D, T
Lec-120 : czcams.com/video/hyx8H-mmr8c/video.html
zhlédnutí: 1 043

Video

T Flip flop | The edge triggered | STLD | Lec-120
zhlédnutí 384Před 14 dny
STLD : Switching Theory and Logic Design The edge triggered T Flip flop Lec-119 : czcams.com/video/xcOwZz28QPI/video.html Lec-121 : czcams.com/video/AZ7QUywdwQI/video.html
J K Flip flop | Edge triggered | STLD | Lec-119
zhlédnutí 315Před 14 dny
STLD : Switching Theory and Logic Design The edge triggered J K Flip flop Lec-118 : czcams.com/video/zceEOvzyYe0/video.html Lec-120 : czcams.com/video/hyx8H-mmr8c/video.html
D flip flop | Edge Triggered | STLD| Lec-118
zhlédnutí 1,4KPřed měsícem
D flip flop | Edge Triggered | STLD| Lec-118
S R Flip flop | Edge triggered | Waveforms | STLD | Lec-117
zhlédnutí 620Před měsícem
S R Flip flop | Edge triggered | Waveforms | STLD | Lec-117
D Latch | Gated | Truth Table | STLD | Lec-116
zhlédnutí 352Před měsícem
D Latch | Gated | Truth Table | STLD | Lec-116
SR latch | Gated | Truth Table | STLD | Lec-115
zhlédnutí 334Před měsícem
SR latch | Gated | Truth Table | STLD | Lec-115
S R Latch | NAND gate | STLD | Lec-114
zhlédnutí 833Před měsícem
S R Latch | NAND gate | STLD | Lec-114
S R Latch | NOR gate | STLD | Lec-113
zhlédnutí 375Před měsícem
S R Latch | NOR gate | STLD | Lec-113
Flip flops | Latches | STLD | Lec-112
zhlédnutí 331Před měsícem
Flip flops | Latches | STLD | Lec-112
Sequential circuits | Classification | STLD | Lec-111
zhlédnutí 304Před měsícem
Sequential circuits | Classification | STLD | Lec-111
PROM | Logic Diagram | Example problem | STLD | Lec-110
zhlédnutí 549Před 2 měsíci
PROM | Logic Diagram | Example problem | STLD | Lec-110
PLA with PLA table | Example problem | STLD | Lec-109
zhlédnutí 300Před 2 měsíci
PLA with PLA table | Example problem | STLD | Lec-109
Design using PLA | STLD | Lec-108
zhlédnutí 257Před 2 měsíci
Design using PLA | STLD | Lec-108
PAL with PAL table | Example problem | STLD | Lec-107
zhlédnutí 266Před 2 měsíci
PAL with PAL table | Example problem | STLD | Lec-107
Design using PAL | STLD | Lec-106
zhlédnutí 239Před 2 měsíci
Design using PAL | STLD | Lec-106
Programmable Array Logic | PLA, PROM | STLD | Lec-105
zhlédnutí 263Před 2 měsíci
Programmable Array Logic | PLA, PROM | STLD | Lec-105
ROM | Types M-ROM, P-ROM, EPROM, EEPROM | STLD | Lec-104
zhlédnutí 257Před 2 měsíci
ROM | Types M-ROM, P-ROM, EPROM, EEPROM | STLD | Lec-104
ROM | Programmable Logic Device | Part-2/2 | STLD | Lec-103
zhlédnutí 244Před 2 měsíci
ROM | Programmable Logic Device | Part-2/2 | STLD | Lec-103
Programmable Logic Device | Part-1/2 | STLD | Lec-102
zhlédnutí 295Před 2 měsíci
Programmable Logic Device | Part-1/2 | STLD | Lec-102
VHDL and Verilog codes | Differences VHDL & Verilog | Digital Design | Lec-18
zhlédnutí 517Před 2 měsíci
VHDL and Verilog codes | Differences VHDL & Verilog | Digital Design | Lec-18
Component declaration and instantiation | VHDL | Digital Design | Lec-17
zhlédnutí 483Před 2 měsíci
Component declaration and instantiation | VHDL | Digital Design | Lec-17
Conditional and selected signal assignment statements | VHDL | Digital Design | Lec-16
zhlédnutí 327Před 2 měsíci
Conditional and selected signal assignment statements | VHDL | Digital Design | Lec-16
Concurrent signal assignment statement | Concurrent Vs Sequential | VHDL | Digital Design | Lec-15
zhlédnutí 379Před 2 měsíci
Concurrent signal assignment statement | Concurrent Vs Sequential | VHDL | Digital Design | Lec-15
Process statement | Case, Null , Loop | Part-2/2 | Digital IC Design | Lec-13
zhlédnutí 413Před 2 měsíci
Process statement | Case, Null , Loop | Part-2/2 | Digital IC Design | Lec-13
Process statement | Variable, Signal, Wait & If | Part-1/2 | Digital IC Design | Lec-13
zhlédnutí 342Před 2 měsíci
Process statement | Variable, Signal, Wait & If | Part-1/2 | Digital IC Design | Lec-13
Operators in VHDL | Logical, Relational | Digital IC Design | Lec-12
zhlédnutí 299Před 2 měsíci
Operators in VHDL | Logical, Relational | Digital IC Design | Lec-12
Data types | Pre-defined type & Scalar type | Part-2/2 | Digital IC Design | Lec-11
zhlédnutí 484Před 2 měsíci
Data types | Pre-defined type & Scalar type | Part-2/2 | Digital IC Design | Lec-11
Data types | Pre-defined type & Scalar type | Part-1/2 | Digital IC Design | Lec-10
zhlédnutí 453Před 2 měsíci
Data types | Pre-defined type & Scalar type | Part-1/2 | Digital IC Design | Lec-10
VHDL | Data objects | Signal & File | Part -2/2 | Digital IC Design | Lec-09
zhlédnutí 395Před 2 měsíci
VHDL | Data objects | Signal & File | Part -2/2 | Digital IC Design | Lec-09

Komentáře

  • @grameshbabu9479
    @grameshbabu9479 Před 6 hodinami

    mam material share cheyochu kada

  • @EnyewM
    @EnyewM Před 6 hodinami

    🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏

  • @SAGANASAGANA-qy3mw
    @SAGANASAGANA-qy3mw Před 7 hodinami

    Thank you so much for explaining dis topic ❤

  • @rakin3333
    @rakin3333 Před 12 hodinami

    First step is not needed. U can avoid it

  • @mallerschwab980
    @mallerschwab980 Před 13 hodinami

    When you don't know where to go you need an indian tutorial. So here we are

  • @user-pd5sq4xr9o
    @user-pd5sq4xr9o Před 13 hodinami

    failure❌ felur ✅

  • @user-qe3st6pu2t
    @user-qe3st6pu2t Před 13 hodinami

    Are yrr hi Hindi me hi bol liya kro jab aati hi nhi ho to 🙏

  • @amittiwary2469
    @amittiwary2469 Před 14 hodinami

    Dabalu😂 ....

  • @moviesflix7082
    @moviesflix7082 Před 15 hodinami

    This video i absolute trash, this lady just read what was written in page with no explanation...Just don't waste your time

  • @amanRG
    @amanRG Před 16 hodinami

    Too slow and useless video😢

  • @amanRG
    @amanRG Před 17 hodinami

    नाईबरस

  • @anandkulkarni3901
    @anandkulkarni3901 Před 18 hodinami

    Watching 1 hr before exam

  • @youtubehub5499
    @youtubehub5499 Před dnem

    Iska basha samjna kaffi mushkil Hain bhaiyaa..

  • @crown6321
    @crown6321 Před dnem

    no meaning of these video

  • @crown6321
    @crown6321 Před dnem

    video is totally out of concept

  • @Xzerox07
    @Xzerox07 Před dnem

    Thank you sir awesome Explanation worth for 8 marks❣️🤩

  • @bollywoodworld1852

    Bullet kon chala raha hein bhai background mein😂

  • @prajothnaik9709
    @prajothnaik9709 Před dnem

    3:00

  • @user-pt4pf7hm4x
    @user-pt4pf7hm4x Před dnem

    ❤❤❤❤

  • @CSEA_58ShayoriBhowmick

    Thank you ❤❤❤

  • @HafsaBibi-be5tv
    @HafsaBibi-be5tv Před dnem

  • @user-fo1et5gd4o
    @user-fo1et5gd4o Před dnem

    Cch hgt

  • @GokhanSahin5228
    @GokhanSahin5228 Před dnem

    thats a battle in 05.14

  • @rc._.naveen
    @rc._.naveen Před dnem

    reduce ❌ red juice ✅

  • @unknownboy-rh1xx
    @unknownboy-rh1xx Před dnem

    What happens if we search element is 12 it between in last step 11 and 12 ,and our last middle search 11 is middle number then how we calculate

  • @rc._.naveen
    @rc._.naveen Před dnem

    reduce ❌ red juice ✅

  • @shivaholicbhaktofmahadev4565

    Nice explanation mam 🥰

  • @user-jl1hl5vo6s
    @user-jl1hl5vo6s Před dnem

    tatti !

  • @MythiliMythili-lm3vs

    Waste of time 😢

  • @newtechnologyandgaming596

    Your explanation is incredable I am following you from 1st year of my engineering jounery ❤🎉

  • @boovananathan8523
    @boovananathan8523 Před dnem

    set speed 1.25 "Set the speed to 1.25."

  • @karthikgururajan1131

    Thanks

  • @tanmaydebnath9011
    @tanmaydebnath9011 Před dnem

    Jab nahi bola ja Raha Hain English tab kue bolte ho aise........Hindi main hi bolo samajh vi Aya ga acche se lekin apni bezati mat karau aise

  • @karthikgururajan1131

    Seeing this an hour before internals xD , Thanks a lot ma’am was pretty useful

  • @narendrasarvepalli

    To day exam button ✅

  • @user-sb6nh1oc4p
    @user-sb6nh1oc4p Před dnem

    Please send the notes mam

  • @user-sb6nh1oc4p
    @user-sb6nh1oc4p Před dnem

    Hi mam

  • @ujjvalverma5358
    @ujjvalverma5358 Před dnem

    1hour from exam

  • @priyanshu8060
    @priyanshu8060 Před dnem

    01:37 Normalization reduces data redundancy 03:14 Normalization reduces data redundancy by eliminating specified dependencies. 04:51 Normalization in databases prevents insert and delete anomalies 06:28 Delete anomalies can cause loss of related attributes and incomplete deletion of records. 08:05 Normalization is a method to remove data anomalies and maintain database consistency. 09:42 Normal forms in database design 11:19 4NF is based on keys and multi-valued dependencies 12:55 Characteristics of normalization are scalar values, minimal null values, absence of redundancy, minimal loss of information Crafted by Merlin AI.

  • @arda4kann
    @arda4kann Před 2 dny

    that was a drive-by shooting 5:04

  • @peaceful891
    @peaceful891 Před 2 dny

    Thankyou ma'am 😊

  • @user-pc7lf9yj4i
    @user-pc7lf9yj4i Před 2 dny

    00:02 RISC emphasizes hardware, CISC emphasizes software 00:41 CISC requires multiple clock cycles for complex instructions 01:00 RISC vs CISC 01:31 Difference between RISC and CISC in pipeline usage 02:02 RISC vs CISC architecture 02:40 RISC and CISC architectures differ in instruction format 03:11 RISC uses only load and store instructions for accessing memory 03:36 RISC vs CISC in memory referencing Crafted by Merlin AI.

  • @user-pj1rq2bd3v
    @user-pj1rq2bd3v Před 2 dny

    Are detailing ke saath complication mat kro or Hindi mein araam se boloo

  • @lazy_boy_0_0
    @lazy_boy_0_0 Před 2 dny

    Brilliant Work ❤❤❤

  • @akashgite905
    @akashgite905 Před 2 dny

    It's the simplest and easiest way of explanation Thank you mam for everything 🙏

  • @fahadnaeem424
    @fahadnaeem424 Před 2 dny

    She even has written many things wrong

  • @user-xs9cq8pk4t
    @user-xs9cq8pk4t Před 2 dny

    Mam aap pls hindi me bola karo jab app english me conversations nhi kr pati hai

  • @HemanthCricketStats

    If we write this in exam marks are give or not??

  • @MrRaj-fl5mm
    @MrRaj-fl5mm Před 2 dny

    Worthy

  • @bunnyblaster5859
    @bunnyblaster5859 Před 2 dny

    Madam e subject important questions chepara