Telugu Engineering
Telugu Engineering
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Parallel Block Statements - Example with Fork-Join || Verilog lectures in Telugu - 34
Parallel Blocks in Verilog.
zhlédnutí: 593

Video

Initial Block Example || Verilog lectures in Telugu - 333:28Initial Block Example || Verilog lectures in Telugu - 33
Initial Block Example || Verilog lectures in Telugu - 33
zhlédnutí 192Před 6 měsíci
Example of Initial Block.
Initial Block || Verilog lectures in Telugu - 323:40Initial Block || Verilog lectures in Telugu - 32
Initial Block || Verilog lectures in Telugu - 32
zhlédnutí 198Před 6 měsíci
Initial is one of the procedural block in verilog.
4-bit Left Shift Register - sequential design || Verilog lectures in Telugu - 313:374-bit Left Shift Register - sequential design || Verilog lectures in Telugu - 31
4-bit Left Shift Register - sequential design || Verilog lectures in Telugu - 31
zhlédnutí 193Před 6 měsíci
Sequential Design Models
4:16 Decoder - sequential design || Verilog lectures in Telugu - 302:554:16 Decoder - sequential design || Verilog lectures in Telugu - 30
4:16 Decoder - sequential design || Verilog lectures in Telugu - 30
zhlédnutí 195Před 6 měsíci
Sequential Design models.
4:16 Decoder - combinational design || Verilog lectures in Telugu - 293:044:16 Decoder - combinational design || Verilog lectures in Telugu - 29
4:16 Decoder - combinational design || Verilog lectures in Telugu - 29
zhlédnutí 174Před 6 měsíci
4:16 Decoder
1:4 Demultiplexer - combinational design || Verilog lectures in Telugu - 273:041:4 Demultiplexer - combinational design || Verilog lectures in Telugu - 27
1:4 Demultiplexer - combinational design || Verilog lectures in Telugu - 27
zhlédnutí 157Před 6 měsíci
1:4 Demutliplexer
Combinational Design - Full Adder || Verilog lectures in Telugu - 274:04Combinational Design - Full Adder || Verilog lectures in Telugu - 27
Combinational Design - Full Adder || Verilog lectures in Telugu - 27
zhlédnutí 145Před 6 měsíci
2:1 MUX is a Combinational design. This video explains about it's design in verilog.
Combinational Design - Full Adder || Verilog lectures in Telugu - 254:36Combinational Design - Full Adder || Verilog lectures in Telugu - 25
Combinational Design - Full Adder || Verilog lectures in Telugu - 25
zhlédnutí 141Před 6 měsíci
Full Adder Design in Verilog.
Combinational Design - Half Adder || Verilog lectures in Telugu - 254:53Combinational Design - Half Adder || Verilog lectures in Telugu - 25
Combinational Design - Half Adder || Verilog lectures in Telugu - 25
zhlédnutí 212Před 6 měsíci
Example of Combinational Design using always block.
Always Block || Verilog lectures in Telugu - 233:13Always Block || Verilog lectures in Telugu - 23
Always Block || Verilog lectures in Telugu - 23
zhlédnutí 239Před 6 měsíci
Know more about verilog always block.
Designing combinational & Sequential design using always block ||4:04Designing combinational & Sequential design using always block ||
Designing combinational & Sequential design using always block ||
zhlédnutí 173Před 6 měsíci
Combinational & Sequential designs using always block with examples.
Concatenation & Replication Operators ||Verilog lectures in Telugu - 223:13Concatenation & Replication Operators ||Verilog lectures in Telugu - 22
Concatenation & Replication Operators ||Verilog lectures in Telugu - 22
zhlédnutí 203Před 6 měsíci
Learn about Concatenation & Replication Operators in this video.
Operators || Verilog lectures in Telugu - 219:33Operators || Verilog lectures in Telugu - 21
Operators || Verilog lectures in Telugu - 21
zhlédnutí 231Před 6 měsíci
Different operators in Verilog.
Assign statements || Verilog lectures in Telugu - 203:13Assign statements || Verilog lectures in Telugu - 20
Assign statements || Verilog lectures in Telugu - 20
zhlédnutí 254Před 6 měsíci
Assign statements || Verilog lectures in Telugu - 20
Module Instantiation - Methods || Verilog lectures in Telugu - 193:58Module Instantiation - Methods || Verilog lectures in Telugu - 19
Module Instantiation - Methods || Verilog lectures in Telugu - 19
zhlédnutí 285Před 6 měsíci
Module Instantiation - Methods || Verilog lectures in Telugu - 19
Ports & It's types || Verilog lectures in Telugu - 183:58Ports & It's types || Verilog lectures in Telugu - 18
Ports & It's types || Verilog lectures in Telugu - 18
zhlédnutí 194Před 6 měsíci
Ports & It's types || Verilog lectures in Telugu - 18
Module & It's purpose || Verilog lectures in Telugu - 179:15Module & It's purpose || Verilog lectures in Telugu - 17
Module & It's purpose || Verilog lectures in Telugu - 17
zhlédnutí 270Před 6 měsíci
Module & It's purpose || Verilog lectures in Telugu - 17
Memories in Verilog || Verilog lectures in Telugu - 163:58Memories in Verilog || Verilog lectures in Telugu - 16
Memories in Verilog || Verilog lectures in Telugu - 16
zhlédnutí 179Před 6 měsíci
Memories in Verilog || Verilog lectures in Telugu - 16
Arrays & Array assignment || Verilog lectures in Telugu - 154:56Arrays & Array assignment || Verilog lectures in Telugu - 15
Arrays & Array assignment || Verilog lectures in Telugu - 15
zhlédnutí 221Před 6 měsíci
Arrays & Array assignment || Verilog lectures in Telugu - 15
Bit-Select & Part-Select | Verilog lectures in Telugu - 144:56Bit-Select & Part-Select | Verilog lectures in Telugu - 14
Bit-Select & Part-Select | Verilog lectures in Telugu - 14
zhlédnutí 214Před 6 měsíci
Bit-Select & Part-Select | Verilog lectures in Telugu - 14
Scalar & Vector | Verilog lectures in Telugu - 134:56Scalar & Vector | Verilog lectures in Telugu - 13
Scalar & Vector | Verilog lectures in Telugu - 13
zhlédnutí 282Před 6 měsíci
Scalar & Vector | Verilog lectures in Telugu - 13
Examples for Data-Types || Verilog lectures in Telugu - 125:10Examples for Data-Types || Verilog lectures in Telugu - 12
Examples for Data-Types || Verilog lectures in Telugu - 12
zhlédnutí 241Před 6 měsíci
Examples for Data-Types || Verilog lectures in Telugu - 12
Integer, real, time, real time|| Verilog lectures in Telugu - 115:10Integer, real, time, real time|| Verilog lectures in Telugu - 11
Integer, real, time, real time|| Verilog lectures in Telugu - 11
zhlédnutí 272Před 6 měsíci
Integer, real, time, real time|| Verilog lectures in Telugu - 11
Identifiers & Keywords || Verilog lectures in Telugu - 75:10Identifiers & Keywords || Verilog lectures in Telugu - 7
Identifiers & Keywords || Verilog lectures in Telugu - 7
zhlédnutí 389Před 6 měsíci
Identifiers & Keywords || Verilog lectures in Telugu - 7
Wire | Datatypes || Verilog lectures in Telugu - 96:18Wire | Datatypes || Verilog lectures in Telugu - 9
Wire | Datatypes || Verilog lectures in Telugu - 9
zhlédnutí 270Před 6 měsíci
Wire | Datatypes || Verilog lectures in Telugu - 9
Nets | Datatypes || Verilog lectures in Telugu - 94:22Nets | Datatypes || Verilog lectures in Telugu - 9
Nets | Datatypes || Verilog lectures in Telugu - 9
zhlédnutí 278Před 6 měsíci
Nets | Datatypes || Verilog lectures in Telugu - 9
Content of the variable & It's significance || Verilog lectures in Telugu - 86:02Content of the variable & It's significance || Verilog lectures in Telugu - 8
Content of the variable & It's significance || Verilog lectures in Telugu - 8
zhlédnutí 266Před 6 měsíci
Content of the variable & It's significance || Verilog lectures in Telugu - 8
Operators and Number Format || Verilog lectures in Telugu - 64:52Operators and Number Format || Verilog lectures in Telugu - 6
Operators and Number Format || Verilog lectures in Telugu - 6
zhlédnutí 506Před 6 měsíci
Operators and Number Format || Verilog lectures in Telugu - 6
Comments & White spaces || Verilog lectures in Telugu - 54:52Comments & White spaces || Verilog lectures in Telugu - 5
Comments & White spaces || Verilog lectures in Telugu - 5
zhlédnutí 671Před 6 měsíci
Comments & White spaces || Verilog lectures in Telugu - 5

Komentáře

  • @AllinOneVolgz
    @AllinOneVolgz Před 6 hodinami

    Copy vedios...don't confuse bro.... explain clearly

  • @PsvssrK-i9o
    @PsvssrK-i9o Před dnem

    Keka puttistannaru sir. Great

  • @user-wc9zz4up3l
    @user-wc9zz4up3l Před 2 dny

    Anna nuv cheppina process ni DIGITAL LOGIC DESIGN ki use cheyochuga like conversations

  • @machamadhu1486
    @machamadhu1486 Před 2 dny

    You taken 6 as 3 3 as. O hw

  • @machamadhu1486
    @machamadhu1486 Před 2 dny

    Tq sir ur explanation spr❤

  • @aadhya4079
    @aadhya4079 Před 3 dny

    Analog layout complet subject and labs videos cheyandi me videos Baga explanation chestaru

  • @aadhya4079
    @aadhya4079 Před 3 dny

    Hi bro meru vlsi lo job chestunara

  • @opgamers5164
    @opgamers5164 Před 4 dny

    Thanks u

  • @Karthik-sw3tv
    @Karthik-sw3tv Před 7 dny

    bro please make videos for polytechnic students of ece branch

  • @bejagamsambasivarao5297
    @bejagamsambasivarao5297 Před 7 dny

    Rac=5 rab= 30 rbc=15 video lo unna values wrong 😂

  • @Vinaybandi07
    @Vinaybandi07 Před 10 dny

    Nice explanation anna❤

  • @nareshabhira8728
    @nareshabhira8728 Před 10 dny

    Thanks

  • @SravanChintunnss
    @SravanChintunnss Před 10 dny

    Channel name is Telugu engineering but you are explaining in English😕

  • @sudhakarvelpuri5592
    @sudhakarvelpuri5592 Před 11 dny

    videos last lo cut avvuthunay bro

  • @user-dv8df6ql6j
    @user-dv8df6ql6j Před 12 dny

    lets go and watch and clear all your doubts in 4min. thank you bro

  • @user-hz8jx3lr6k
    @user-hz8jx3lr6k Před 13 dny

    Increment operator and decrement operator explain cheyandi

  • @shashikalashashikala3089
    @shashikalashashikala3089 Před 14 dny

    Tq u sir

  • @Ashok56347
    @Ashok56347 Před 15 dny

    Sir can i watch the whole playlist for my btech 1st year 2nd sem regular exam is it useful pla reply sir😊😊😊

  • @SuryaKiran2251
    @SuryaKiran2251 Před 16 dny

    Great explanation 🎉🎉❤

  • @SuryaKiran2251
    @SuryaKiran2251 Před 16 dny

    Brother,telugu lo electronics and communication cheppandi , govt technical ga prepare ayyevallaki use avuthundhi

  • @varshakarani8966
    @varshakarani8966 Před 18 dny

    Tq

  • @user-wo9oq8rg9v
    @user-wo9oq8rg9v Před 19 dny

    Sir can you please explain in xilinx software for your practical exams please 🙏🏻sir . Your teaching is very nice sir

  • @RamyaNanubothu
    @RamyaNanubothu Před 19 dny

    If we take s0=0,s1=1,s2=0,s3=0 what is out put sir in 16:1mux

  • @AKSHITHAPANDILLAPALLI
    @AKSHITHAPANDILLAPALLI Před 22 dny

    Hoiii mowaaa 🎉

  • @user-ho5kd7dv4e
    @user-ho5kd7dv4e Před 23 dny

    Mam if sum is equal to 9 if carry generated then we have to add 6 in that case or not

  • @Leo_naidu
    @Leo_naidu Před 23 dny

    Very clear

  • @Manjusree-kj8vq
    @Manjusree-kj8vq Před 24 dny

    Ma devudu nuvvenayya Ma kosam puttavayya 🔥🔥

  • @TeluguTruckGaming.0412
    @TeluguTruckGaming.0412 Před 25 dny

    Bad😂 explanation 😂😂😂

  • @user-yp5oo8ey8e
    @user-yp5oo8ey8e Před 26 dny

    P channel e mosfet same vuntadaaa n channel ki

  • @ravulapalli7294
    @ravulapalli7294 Před 27 dny

    Super sir

  • @TejaswiniGajulapalli
    @TejaswiniGajulapalli Před 29 dny

    I’ve been watching all your videos on verilog, I’m excited to ask you about system verilog lectures , how can I contact you??

  • @TejaswiniGajulapalli
    @TejaswiniGajulapalli Před 29 dny

    How can I contact you ?

  • @TejaswiniGajulapalli
    @TejaswiniGajulapalli Před 29 dny

    bruh!!!!! okasari reply evvara, system verilog telugu lo explain cheyyagalara? elage neat and clean ga

  • @TejaswiniGajulapalli
    @TejaswiniGajulapalli Před 29 dny

    system verilog meedha kuda videos chesthey, students ki use ayithadhi andi

  • @harshireddy8025
    @harshireddy8025 Před 29 dny

    Each video will be cut at the end of the part please upload full video

  • @Pavansai-bc5os
    @Pavansai-bc5os Před měsícem

    Signs use chestu apply cheyyandi madam

  • @sandeepnani2089
    @sandeepnani2089 Před měsícem

    Thankyou mam❤

  • @SathwikReddy-xm2up
    @SathwikReddy-xm2up Před měsícem

    Jai supplie

  • @padhuuu
    @padhuuu Před měsícem

    Chala Baga aa chepparu thank you so much 🥰

  • @santhoshdhannana963
    @santhoshdhannana963 Před měsícem

    Memu govt technical prepare avutunnamu maku telugu lo technical channels levu..meru electronics and communication gurunchi chepte ma lanti chala Mandi useful avutundi...kindly request anna

  • @santhoshdhannana963
    @santhoshdhannana963 Před měsícem

    Hi anna

  • @santhububly2215
    @santhububly2215 Před měsícem

    Ur explanation is 👌 sir..ila chepthe electrical subject easy ga anipistundi. Keep going sir.

  • @user-hu3lw7nd2c
    @user-hu3lw7nd2c Před měsícem

    Wonderful job dear brother.. I was excited seeing this VLSI Telugu channel. Love you, it will be helpful to thousands of students. thank you so much for your initiative.

  • @youaremyinspirationYOUTUBE
    @youaremyinspirationYOUTUBE Před měsícem

    Thank you so much sir 🙏

  • @shwethap-oc3ni
    @shwethap-oc3ni Před měsícem

    ❤❤

  • @gidyonumerla-jx8ln
    @gidyonumerla-jx8ln Před měsícem

    Anna ee chapter lo formulas and problems medha videos chey anna.baga cheptunaru meeru.

  • @NAIDUSGAMEINGYTFF
    @NAIDUSGAMEINGYTFF Před měsícem

    4

  • @Raina__Roy____143
    @Raina__Roy____143 Před měsícem

    Very well explained 👍

  • @user-mh7bz5th8j
    @user-mh7bz5th8j Před měsícem

    Telugu lo cheppandi please asalake ee subject ardham kadhu malli English enti

  • @user-kt7od3rq3v
    @user-kt7od3rq3v Před měsícem

    bro miru super Mah faculty cheppedi m ardam avaledu maku Mih videos dwara understand well bro Tq...