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BYU Computing Bootcamp
Registrace 29. 03. 2021
Welcome to our CZcams channel for BYU's Computing Bootcamp! This channel is dedicated to helping you build important skills with coding and computers. Videos are comprised of Zoom recordings from the lecture series the BYU Electrical and Computer Engineering department does for their research program IMMERSE each summer.
Video
Docker (2022)
zhlédnutí 244Před 2 lety
0:00 Background 7:50 Docker vs. VM and WSL 12:47 WebCrawler Example 18:06 Send Code to Server 28:07 Create Docker Image 34:33 Run Docker Image 45:36 Code to Server via Docker 51:12 Reduce Storage Size
Vitis HLS
zhlédnutí 11KPřed 3 lety
0:00 Introduction to High Level Synthesis 8:20 Example function 10:39 Introduction to Vitis HLS 17:43 C Simulation 20:15 C Synthesis 28:30 Seeing the generated Verilog 32:42 Thoughts on increasing the performance 38:19 Using Vitis HLS to optimise performance 57:28 Using main memory
Vivado and Vitis
zhlédnutí 13KPřed 3 lety
0:00 Introduction 8:44 Introduction to block design and hardware configuration 29:34 Preparing and generating a bitstream 42:58 Introduction to Vitis and exporting from Vivado 47:52 Example Vitis project
Networking command line tools
zhlédnutí 767Před 3 lety
0:00 Introduction 1:19 ifconfig and ip address 6:59 ping 10:34 dig and nslookup 16:18 traceroute 21:05 curl/wget/httpie 30:04 arp 31:53 nmap 37:28 nc 40:38 tcpdump/wireshark/tshark 52:06 Wrap-up
Symbiflow exploration and Symbiflow-examples
zhlédnutí 501Před 3 lety
Symbiflow exploration and Symbiflow-examples
powerful tools for fpga
What i want to know is what else di they do un Celestial Heaven, besides vigorously engaging in purely spiritual procreational.
Woah, for a second there thought that it was Jordan Peterson. Like Jordan knows FPGAs too? Voices IMHO pretty similar 😛
lmfao
@@ffdm Am I right? Maybe both are Canadian :-P
@@joeneighbor Yeah they definitely sound similar lol
the microphone seemed to move from the speaker
Respect for bitstream generation reinstated! Thanks for the fundamentals. Are engineering lectures available online?
Thanks Sir!
I might use a Mecano anaolgy here. If we pretend for a second that Mecano was all there was: A CPU would be like a tape-based music box (built out of Mecano... yeh, bear with it). It's all welded together, so you can't change the mechanism, and provided you feed it the right punched tape it will make great-sounding soft music. An ASIC would be a special music box, maybe it has less range, maybe it has a few more harps, but the music is on a steel drum. Again, all the Mecano bits are welded together, so can't be changed. It plays that one song and it plays it really well. An FPGA, in contrast, is just a box of Mecano parts (sub-assemblies really). Go build what ever you want ;)
Hmm... wouldn't it be sensible for a write-once offering to have a rewritable counterpart for testing purposes? Especially when they come with a $100k price tag...
Thanks a lot!👍
These lectures are so valuable! Thank you!
Thk-you Thk-you
Thk-you Thk-you
Super helpful and informative, thank you (y)
Thanks. This does help me understand why it takes so long to synthesize the simple designs I’m experimenting with. Great video.
Great job!
Thanks!
what is the 220 course that's mentioned in this video?
Nice tutorial.. Can you tell me which debugger are you using for programming and debugging in this video? Which one is good to use for multiple CPU's and FPGA core debugging?
What an amazing lecture, thoroughly enjoyed it, and learned a ton!
Extremely good video. Thank you
I can’t synthesize why? Using your version too.
Hello, Can I have the working code for the vitis please
Hi, good lecture. I'm just curious what was the book used in this lecture called "v2.0 Posted"?
me too
BUMP
How do I migrate the HLS Video Library onto the Vitis Vison Library?
Does Vitis HLS v2022.1 support built-in HLS Functions such as hls::Threshold, hls::Erode, hls::Dilate, hls::Mul, hls::Duplicate, hls::MinMaxLoc, hls::CvtColor etc. ?
58:03 this indentation is a test to my ocd...
47:00
Very good introduction! I currently add Kintex support for prjxray and this is great to introduce new contributors!
Thanks for putting this together!
Did you find the error? What was the fix?
For one thing, he used _BASEADDR instead of _DEVICE_ID with XGpio_Initialize().
In addition to John's comment, use 1 for the GPIO Channel.
It turns out you can see the completed code at the beginning of the BYU Computing Bootcamp Vitis HLS video.
@@johnjj2637 bro, in the libary "xparameters.h", there only XPAR_AXI_GPIO_0_BASEADDR, no _DEVICE_ID was declared there
The best tutorial for beginers on HLS ! Fun to watch and i understood every bit of information. Keep doing it ! Great work !
can you do one about cmake and can you do a lot of c++ embedded tutorials i really enjoy them
Great Job!
Please I want frame buffer code in c++
This is the best tutorial on the internet on HLS and optimizations! Thank you for sharing this!
Interesting talk! Did the guest speaker allow his talk to be reposted?
hi