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Very interesting project

I really like the look of that construction. what pcb material did you use for the positive bus bar? It looks a lot thinner than normal clad pcb.

Most interesting - Thanks for putting it "out there" :)

I bought nandland simplified FPGA. He has tutorials on his channel too. Haven't gotten into it yet because there I am on a Mac and there is no version of Ice. I applied for a personal license and havebn't gotten one yet in email -- maybe holidays.

Excellent video !!! Thank you for your work. It help really helped me understand better Verilog HDL and how to make a CPU.

I built all of Ben Eater’s projects, and I’d love to learn an FPGA that doesn’t use Vivado so I’m going to love this. I even bought a copy of that Malvino book. Oh it appears you don’t answer questions and/or share the files you said you’d share, unfortunately. However! It appears we can just take screenshots after all.

Sweet Jesus! Talk about jumping in at the deep end!!! Slow down and explain things - certainly not beginner friendly

Very nice explanation and very usefully and thanks for serving community

tda2822M is used very often has 2 channels which can be bridged. If you want to do discrete transistor 8050 8550 is a great pair. also used a thermally compensated bias with a pot and a sense transistor. 3-5 ma bias is enough. Opamp is not needed at all. just 1 single transistor can drive it . May want to bootstrap load resistor for driver transistor.

sorry for a stupid question, but what is the purpose of R10?

Fantastic! I've wanted to do this exact project t teach myself verilog. I am super limited with switches and indicators on my TinyFPGA Bx lattice board. Does anyone know if there's an equivalent to the in system sources and probes tool for the Ice storm tool chain? I'm using Ice studio. Can I use a tool from outside this toolchain?

Hi there, I got an error at statement of 171 of " assign w_bus = (a_enable) ? SW[7:0] : 8'bZZZZZZZZ; " the problem was w_bus is assigning on multiple therefore I've make it as previous, in which change a_enable with a_latch, my question is that correct please ???

The videos was very pleasant and I'm very enjoyed with you; please complete the SAP design to the end, and continue implementation of your 8-bit computer however we still waiting the upgrading to 16-bit computer, thanks in advance for your explain and interpretation . Kindly Regards Aljshamee

I really hope you continue the series!

Excellent video, excellent explanation, I loved the way you explain how to program in verilog

You don't share your files so, although I am happy for you that you can do this, I would rather learn how and be able to follow along or buy a kit or something. As is, this is just a waste of my time watching someone else do what I would like to but cannot because I am not given the source.

Це є великий клас

Using in and out ports does that result in using different resources in the fpga? Tri-state buffers for example. And are these limited in availability

It looks like you're calling these registers latches. what differentiates a latch from a flip flop?

cool

Another 3 months from the last, and 10 months from the first, I really do hope this series continues.

Very nice video. You go super duper fast, especially for someone with 0.0 knowledge of FPGAs. Not a complaint, just feedback.

You mentioned you would make your verilog code available but I do not see any link. Could I please get a copy? I am trying to follow along and have a de2-70 so the code should be easily refactored. Possibly putting the quartus verilog files on a github site?

Looking forward to following this. I have a de2-70 and a couple other fpga dev boards and want to get back into hdl programming. Can you please tell me the verilog extension you are using in vs code? If you also program in vhdl and could suggest a code extension for that it would be appreciated. Thanks

For those opening these or the larger 2x2 version, there are really good tools for opening them. Two groove pliers, opened wide, and clamped near the bottom, will crack them open very easily. You can use a small pry bar flat curved end to pop them out of the case and I've also used an arrow staple puller. You can assembly line this job and achieve very large volume much quicker. I still hate the process of remove the spot welded strips. Flush cutters are the best so far, but it still sucks.

I think R6 and C2 are redundant. The output of the first stage is at the correct DC bias to connect directly to the second stage.

Back 6 months later... Hopeful that there would be more? 😢

I didn't know we got that kind of command line access in Vivado, thanks!

Tda2822. 8 pins IC. 2channel 2x1watt or. 1x3watt. Work from 3 to 18 volt. Cost. 3 US dollar. ..

Would it be possible to release the Quartus project files at GitHub or somewhere so that people can download and study it?

I remember using a 741 as a simple amp some 50 years ago.

Very interesting video. Thank you. (I just subscribed.)

Hey! I am crazy interested in this and I got myself an Altera board to follow up. Sadly I noticed you haven't uploaded in a long time, so I hope you would continue with this series, as soon as you get the chance again! I am an Elec. Engineer and all about circuitry, MCUs and now thanks to you also FPGAs!

Thanks for the video, it didn't occur to me that the ubiquitous 386 would be put out to grass but it happens to us all in the end. Newbie question, what would be the nearest drop in replacement/alternative when a schematic calls for an LM 386?

Hi Phil, very good instructive video's, when are the next video's coming ?.

awesome content!! please, keep it coming!!

thanks

Awesome videos! Thanks for posting these. I can't wait to see the rest, like naikrovek said, super dense stuff, I watched the first one about 5-6 times following along with a go-board and de0-nano. Probably gonna watch the part where you dive into the ALU on this one about 10 times lol Thanks again!

Are any more of these coming? I really hope so!

Super useful series! Subscribed for more of the same!

Buf634 saves everybody

One diode between the transistor bases halves the slewrate requirements.

Nice use of cad to design manhatten boards

Thank U for this video. By the way there is a lot of IC's which considered very good with less components as well as it has a wider operation voltage rang Such as TBA820m , TDA7052 , TDA2822 TDA7231 , TA7331 , TA7368 , CD7368 , LM4871 , FM8002a and the powerful TA7252AP

these vids are awesome. so dense and so complete. excellent stuff.

I don't think you need R9. Unless I'm missing something, I don't see it doing anything useful. I'm also worried that U1B is going to have stability problems. My quick suggestion would be to have a series resistor between its output and the bases of the transistors. (My gut says 47R to start.) I'd also add a small value capacitor as direct feedback from the output to the inverting input. It may be fine now, but I think you'll get oscillations if you use an opamp with a higher GBP. When using op-amps with output boost stages in the feedback loop, you need to keep the GPB of the op-amp lower than that of the boost stage. However, it's working for you, so my suggestions could be unnecessary. :D

I love the dub-ah-yah bus. 😊

Hi Phil, what are the extensions used for Verilog in 'vscode'?

Интересный материал, но не на русском. И переводчик технический не осилит.

A couple of diodes between the bases of the output transistors, with a trimmer resistor across them to set idle current, would eliminate most all of your crossover distortion. Keep in mind that the fast slews of the op-amp trying to eliminate the crossover distortion (caused by running the output transistors in pure class B) might well create noise in your receiver. This would disappear with my suggested change, which converts the output stage to class AB.