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Semiconductor Engineering
United States
Registrace 27. 06. 2011
System-Level Design, Low-Power/High-Performance Engineering and Semiconductor Manufacturing & Design are focused on deep technology and business issues in semiconductor design, implementation, integration and manufacturing.
Promises And Pitfalls Of SoC Restructuring
As chips become more complex and increasingly heterogeneous, it's becoming more difficult to keep track of different methodologies, tools, and blend data from different sources to create a chip. Tim Schneider, staff application engineer at Arteris, talks with Semiconductor Engineering about why IP-XACT has become so critical, why it took so long to gain a solid foothold in chip design, and how the new IP-XACT standard interfaces with SystemVerilog.
zhlédnutí: 294
Video
Making Adaptive Test Work Better
zhlédnutí 270Před 16 hodinami
One of the big challenges for IC test is making sense of mountains of data, a direct result of more features being packed onto a single die, or multiple chiplets being assembled into an advanced package. Collecting all that data through various agents and building models on the tester no longer makes sense for a couple reasons - there is too much data, and there are multiple customers using the...
MCU Changes At The Edge
zhlédnutí 786Před 14 dny
Microcontrollers are becoming a key platform for processing machine learning at the edge due to two significant changes. First, they now can include multiple cores, including some for high performance and others for low power, as well as other specialized processing elements such as neural network accelerators. Second, machine learning algorithms have been pruned to the point where inferencing ...
Electromigration And IR Drop At Advanced Nodes
zhlédnutí 677Před 21 dnem
Manufacturing chips at 3nm and below is a challenge, but it's only part of the problem. Designing chips that can be manufactured and will actually work is potentially an even bigger problem. There is more data to sift through for place-and-route, less margin to pad a design, and there are more physical effects to contend with as transistors get taller, density increases, and chips age. Jeff Wil...
Adapting To Evolving IC Requirements
zhlédnutí 395Před měsícem
As chip designs become increasingly heterogeneous and domain-specific, packing a device with one-size-fits-all chips or chiplets doesn't make sense. The key is rightsizing different components based on real workloads, so they don't waste power when there is too little utilization of logic, and so they don't struggle to complete tasks because they are undersized. Jayson Bethurem, vice president ...
Sensor Fusion Challenges In Automotive
zhlédnutí 564Před měsícem
The number of sensors in automobiles is growing rapidly alongside new safety features and increasing levels of autonomy. The challenge is integrating them in a way that makes sense, because these sensors are optimized for different types of data, sometimes with different resolution requirements even for the same type of data, and frequently with very different latency, power consumption, and re...
Overlay Optimization In Advanced IC Substrates
zhlédnutí 653Před měsícem
Overlay is becoming a significant problem in the manufacturing of semiconductors, especially in the world of advanced packaging substrates - think panels - the larger the area, the greater the potential for distortion due to warpage. Solving this issue requires more accurate models, better communication through feed forward/feed back throughout the flow, and real-time analytics that are baked i...
Secure Movement Of Data In Test
zhlédnutí 300Před 2 měsíci
Historically, test data flowed out of the tester and was loaded into a file. But with heterogeneous integration, including chiplets and IP from multiple vendors, test data is now being streamed across the manufacturing floor where it can be used to make real-time decisions. Eli Roth, product manager for smart manufacturing at Teradyne, talks with Semiconductor Engineering about challenges in da...
Challenges With Chiplets And Power Delivery
zhlédnutí 1,3KPřed 2 měsíci
Chiplets hold the potential to deliver the same power, performance, and area benefits as an SoC, but with many more features and options that are possible on a reticle-constrained die. If chiplets live up to the hype, they will deliver what is essentially mass customization, democratizing and speeding the delivery of complex chips across a broad array of markets. Today, the focus has been on di...
Challenges In RISC-V Verification
zhlédnutí 980Před 2 měsíci
Designing a single-core RISC-V processor is relatively easy, but verifying it and debugging it is a different story. And it all becomes more complicated when multiple cores are involved, and when those cores need to be cache-coherent. Ashish Darbari, CEO of Axiomise, talks with Semiconductor Engineering about using assertions and formal verification technology to find bugs and prove coherency i...
Cache Coherency In Heterogeneous Systems
zhlédnutí 754Před 2 měsíci
Until recently, coherency was something normally associated with DRAM. But as chip designs become increasingly heterogeneous, incorporating more and different types of compute elements, it becomes harder to maintain coherency in that data without taking a significant hit on performance and power. The basic problem is that not all compute elements fetch and share data at the same speed, and syst...
Rethinking Chip Economics
zhlédnutí 1,1KPřed 2 měsíci
As process nodes shrink, so does the selection of chips developed at those nodes. Consumers demand more features and functionality, but that carries a high price tag in terms of both complexity and real dollars. In addition, because costs are skyrocketing, there is growing pressure for those chips to remain reliable and up-to-date for longer periods of time. Jayson Bethurem, vice president of m...
Cost And Quality Of Chiplets
zhlédnutí 1,4KPřed 2 měsíci
Chiplets add a whole new challenge for the semiconductor industry. How much testing is enough? How do you optimize system binning? What’s the right amount of burn-in? The answers to these questions will vary, depending upon cost and quality tradeoffs, the number and source of the chiplets, and real-world workloads and projected lifespans. Marc Jacobs, senior director of solutions architecture a...
Changes And Challenges In Auto MCUs
zhlédnutí 685Před 3 měsíci
Microcontrollers have been a key component in automotive for years, starting with single-core devices with limited on-chip memory for very basic functions, and evolving toward multi-core systems with more memory for more complex tasks. But as vehicles become increasingly automated, microcontrollers are changing significantly, and so is the perception of how to utilize them. These new devices ne...
Integration Challenges For RISC-V Designs
zhlédnutí 836Před 3 měsíci
One of the big draws of RISC-V is that it allows design teams to create unique chips or chiplets and to make modifications to the instruction-set architecture. That extra degree of freedom also creates some issues when it comes to integrating those designs into packages or systems because they may require non-standard connectivity approaches. Frank Schirrmeister, vice president of marketing at ...
Using Deep Data For Improved Reliability Testing
zhlédnutí 356Před 5 měsíci
Using Deep Data For Improved Reliability Testing
Very Short Reach SerDes In The Data Center
zhlédnutí 686Před 6 měsíci
Very Short Reach SerDes In The Data Center
What To Do About Electrostatic Discharge In Chips
zhlédnutí 1,2KPřed 6 měsíci
What To Do About Electrostatic Discharge In Chips
This is great to watch because my PhD thesis work is on cryogenic MRAM for embedded quantum computing hardware. Thanks for the video :D
Lot of hand waving. Such is the beast the cloud is. Very fluffy and vague vapor. This was five years ago. Things have moved a lot in these five years. I hop you do another video on where we are now on this issue.
Where can I get a tsmc28nm HBM phy?
Great video!! Thanks!
Thx for sharing Doctor Fried. Do we use "Mahalanobis Distance", etc. to optimize "Process Window Optimization"?
Fantastic, but l have aquestion How l use inkjetprinting for printing sensors
What about interface considerations? Do you design for specific interfaces?
I have an solid state analog transmitter of 85 Kw (LARCAN) working uninterrupted for almost 35 years. I am really impressed about how these MOSFET(MRF151G) are still working at maximum RF power without any kind of maintenance.
A GPU made with HMB memory for working memory and GDDR6 memory for a second teir of working memory and background memory. a graphics card like this would be so fast.
Hello there, Analog layout engineer here and I’m watching this in 2024😂, fuck the future robots who gonna replace VLSI engineers,
@2:25 T0 - T1 ? -> since we are talking about Delta on arrival times, should it not be negating, rather than adding? Thanks much for the video !
Density is becoming an issue with reliability. Too much density causes bit flips
Not enough videos and documentation explaining these techniques . Thank you for uploading
Great. AI Clusters seems to be limited by GPU memory and rack bandwidth, so an increasing fraction of silicone and power will go into communication. So great to hear that optics can save a lot of power.
interesting. SO moving from tripling the whole computer , to tripling the critical parts in the IC and leveraging development for faults tolerance from automotive chips.
I was taught to be almost paranoid with ESDs when handling chips and boards, but hearing how much engineering goes into the indented discharge paths goes, explain why people being more casual with their handling still are able to build working devices.
Insightful
Superb
Thank you for your input. This video helped me understand where I need to focus my effort as a backend engineer for timing related issues.
Next video why chips age
Great stuff gentlemen. From a custom fiber cable assembly house perspective, this is very interesting
Very informative!
Great that we get this for free! Have seen some really interesting ideas in this space
How to add this SDC to the simulation?
Super interesting and informative video, thanks!
Very interesting considerations to think about. Many thanks 🙏
I will sleep less ignorant today.
Thanks for visiting us Ed, and looking forward to many future discussions!
This looks like cut tree and partitioning
Great insight 👍
Wow! What about SMEE?
Excellent Video. Shed light on a few things I was wondering about. Well explained.
Thank you for this wonderful explanation
thanks for you guys's effort to this great video.
Does the fact that high NA EUV is anamorphic mean on axis has higher resolution than the other?
Very interesting technology explanation - awesome
thanks for posting this
So we gotta update the routing algorithms for curvy linear design
Interesting 😀
Wow!
Great video. Helped a lot !!
great video, thx
I want this project
its work jumping curent
Very good work
Pim
Thanks for the informative video
damn!
Cool
Thank you.